Open tmeissner opened 7 years ago
Collecting assertion statistics is also a requirement for VHDL-2017.
Questions:
I don't know why the name syntax is different, I took it from an example PSL coverage report. Counting passes & fails separately would be good. So you would know, if your assert statements were covered, even if they don't fail.
Do you need reports for both concurrent and sequential assertions or only for concurrent asserts ? (The later would be much simpler)
I'm honest, both would be good. But if concurrent ones are much simpler, you could implement the immediate ones later. Maybe we also should have a discussion if we should merge all these coverage statistics in one report file and its concrete structure. Like (but not similar) UCDB, or better saying: the export of all coverage information in one single (JSON, XML or whatever) file. This would make the development of a post-simulation Analyse tool/script much more easier.
Is there any progress on this feature request?
It would be nice, if you have a file which includes information about all VHDL assertions after simulation. It could be similar to the file generated for PSL with the --psl-report option.
Included items could be:
Maybe, the PSL report could be merged with this one. Then, the language should also be included in the report file.
An example: