QUADSPI internal timing criticality
Description
The timing of some internal signals of the QUADSPI peripheral is critical. At certain conditions, this can lead to a
general failure of the peripheral. As these conditions cannot be exactly determined, it is recommended to
systematically apply the workaround as described.
Workaround
The code below have to be executed upon reset and upon switching from memory-mapped to any other mode:
// Save QSPI_CR and QSPI_CCR values if necessary
QSPI->QSPI_CR = 0; // ensure that prescaling factor is not at maximum, and disable the perip
heral
while(QSPI->QSPI_SR & 0x20){}; // wait for BUSY flag to fall if not already low
QSPI->QSPI_CR = 0xFF000001; // set maximum prescaling factor, and enable the peripheral
QSPI->QSPI_CCR = 0x20000000; // activate the free-running clock
QSPI->QSPI_CCR = 0x20000000; // repeat the previous instruction to prevent a back-to-back dis
able
// The following command must complete less than 127 kernel clocks after the first write to t
he QSPI_CCR register
QSPI->QSPI_CR = 0; // disable QSPI
while(QSPI->QSPI_SR & 0x20){}; // wait for busy to fall
// Restore CR and CCR values if necessary
For the worakround to be effective, it is important to complete the disable instruction less than 127 kernel clock
pulses after the first write to the QSPI_CCR register
Memory-mapped read of last memory byte fails
Description
Regardless of the number of I/O lines used (1, 2 or 4), a memory-mapped read of the last byte of the memory
region defined through the FSIZE[4:0] bitfield of the QUADSPI_DCR register always yields 0x00, whatever the
memory byte content is. A repeated attempt to read that last byte causes the AXI bus to stall.
Workaround
Apply one of the following measures:
• Avoid reading the last byte of the memory region defined through FSIZE, for example by taking margin in
FSIZE bitfield setting.
• If the last byte is read, ignore its value and abort the ongoing process so as to prevent the AXI bus from
stalling.
• For reading the last byte of the memory region defined through FSIZE, use indirect read
Palomino34
commented
6 months ago
https://www.st.com/resource/en/errata_sheet/[es0392-stm32h742xig-stm32h743xig-stm32h750xb-stm32h753xi-device-errata-stmicroelectronics.pdf](https://www.st.com/resource/en/errata_sheet/es0392-stm32h742xig-stm32h743xig-stm32h750xb-stm32h753xi-device-errata-stmicroelectronics.pdf)
QUADSPI internal timing criticality Description The timing of some internal signals of the QUADSPI peripheral is critical. At certain conditions, this can lead to a general failure of the peripheral. As these conditions cannot be exactly determined, it is recommended to systematically apply the workaround as described. Workaround The code below have to be executed upon reset and upon switching from memory-mapped to any other mode: // Save QSPI_CR and QSPI_CCR values if necessary QSPI->QSPI_CR = 0; // ensure that prescaling factor is not at maximum, and disable the perip heral while(QSPI->QSPI_SR & 0x20){}; // wait for BUSY flag to fall if not already low QSPI->QSPI_CR = 0xFF000001; // set maximum prescaling factor, and enable the peripheral QSPI->QSPI_CCR = 0x20000000; // activate the free-running clock QSPI->QSPI_CCR = 0x20000000; // repeat the previous instruction to prevent a back-to-back dis able // The following command must complete less than 127 kernel clocks after the first write to t he QSPI_CCR register QSPI->QSPI_CR = 0; // disable QSPI while(QSPI->QSPI_SR & 0x20){}; // wait for busy to fall // Restore CR and CCR values if necessary For the worakround to be effective, it is important to complete the disable instruction less than 127 kernel clock pulses after the first write to the QSPI_CCR register
Memory-mapped read of last memory byte fails Description Regardless of the number of I/O lines used (1, 2 or 4), a memory-mapped read of the last byte of the memory region defined through the FSIZE[4:0] bitfield of the QUADSPI_DCR register always yields 0x00, whatever the memory byte content is. A repeated attempt to read that last byte causes the AXI bus to stall. Workaround Apply one of the following measures: • Avoid reading the last byte of the memory region defined through FSIZE, for example by taking margin in FSIZE bitfield setting. • If the last byte is read, ignore its value and abort the ongoing process so as to prevent the AXI bus from stalling. • For reading the last byte of the memory region defined through FSIZE, use indirect read