gicking
commented
6 years ago Hello blkhawk,
checking the reference manuals for STM8S / STM8A (RM0016) and STM8L (RM0031) I realized the are big differences (at least) in the CLK_PCKENR* registers :-( I guess (hope) that this is the cause of the issue you observed, and not a completely different handling of SFRs…
As for a solution: in mid-term I plan to develop device headers also for the non-STM8S/A families. Looking to the SPL by STM I guess I will end up with 4 different header files. Unfortunately that doesn’t help you today…
blkhawk
Found another one. Unless the stm8l152 I am working with is a reversed bit order the order of control bits is revered in your definition. This affects other registers as well.
Timer 3 is working for me now.
/* Peripheral clock gating register 1 (CLK_PCKENR1) / union { /// bytewise access to register uint8_t byte; /// bitwise access to register struct { uint8_t PCKEN_TIM1 : 1; ///< clock enable TIM1 uint8_t PCKEN_TIM3 : 1; ///< clock enable TIM3 uint8_t PCKEN_TIM2_TIM5 : 1; ///< clock enable TIM4/TIM6 uint8_t PCKEN_TIM4_TIM6 : 1; ///< clock enable TIM4/TIM6 uint8_t PCKEN_UART2 : 1; ///< clock enable UART2 uint8_t PCKEN_UART1 : 1; ///< clock enable UART1 uint8_t PCKEN_SPI : 1; ///< clock enable SPI uint8_t PCKEN_I2C : 1; ///< clock enable I2C } reg; } PCKENR1;