Last data when using trigger

[tmk]

I'm using this logic_analyzer with Arduino Uno and jawi/ols client and found the client get one incorrect data at the very last. This happens when using trigger with sampling rate 500khz(or less), or when triggerMicro() is executed.

Following two pictures show the issue. See glitch in signal of Channel-0 and 1 at the very last(rightmost). The last sampling data shown at the rightmost is not placed correctly. And I believe the data should be palced in the first position, or at the leftmost. (These are Sampling rate and Trigger setting.)

I think this part of triggerMicro() causes the issue and it seems to be not needed to me. This patch solves this issue. But I'm not sure this is right solution, or am I missing something?

diff --git a/logic_analyzer/logic_analyzer.ino b/logic_analyzer/logic_analyzer.ino
index 2daaa42..e3c7b68 100644
--- a/logic_analyzer/logic_analyzer.ino
+++ b/logic_analyzer/logic_analyzer.ino
@@ -878,16 +878,6 @@ void triggerMicro() {
   /* re-enable interrupts */
   sei();

-  /*
-   * trigger has fired and we have read delayCount of samples after the
-   * trigger fired.  triggerIndex now points to the trigger sample
-   * logicIndex now points to the last sample taken and logicIndex + 1
-   * is where we should start dumping since it is circular.
-   *
-   * our buffer starts one entry above the last read entry.
-   */
-  logicIndex++;
-
   for (i = 0 ; i < readCount; i++) {
     if (logicIndex >= readCount) {
       logicIndex = 0;

https://github.com/gillham/logic_analyzer/blob/master/logic_analyzer/logic_analyzer.ino#L881-L889

No glitch with the patched firmware.