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gmcastil / basys3

A collection of source code and build scripts targeting the Digilent Basys3 FPGA board
MIT License
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Finish the UART RTL and verify in simulation #3

Closed gmcastil closed 2 months ago

gmcastil commented 3 months ago

The TX side seems to be working (TX meaning, data from Basys3 to PC) and RX has been implemented, but has sufficient bugs that it gets uprooted during synthesis. Need to track down why that is in simulation, fix it, finish the code. The portion of code that actually reads from the UART is incomplete because I'm not sure how I want to handle the case of data being received and needing to put it somewhere. Obviously, a FIFO is the right answer, but not sure where I want to put it yet. I'm leaning towards outside the UART, so that it doesn't have to simulate or be used with Xilinx IP or XPM or whatever.

gmcastil commented 2 months ago

Fixed this - rewrote basically everything, now that I understand the way that the RX should work. Next up will be adding FIFOs to the TX and RX side.