Currently there is support for flowing data in and out of HDL but no control support. Verilator supports directly modifying register values which could be a simple approach here.
It would (probably?) be asynchronous so there an example of wrapping a raw external register with a clock domain crossing is probably useful.
Currently there is support for flowing data in and out of HDL but no control support. Verilator supports directly modifying register values which could be a simple approach here.
It would (probably?) be asynchronous so there an example of wrapping a raw external register with a clock domain crossing is probably useful.