This is part of being able to handle bursts of data. Supporting sob and eob for starting and stopping transactions on the HDL buses would be really valuable. Some consideration of how clocking would work when samples are not passing is needed I think.
Originally requested by @gs-jgj at https://github.com/B0WEN-HU/gr-verilog/issues/4
This is part of being able to handle bursts of data. Supporting
sobandeobfor starting and stopping transactions on the HDL buses would be really valuable. Some consideration of how clocking would work when samples are not passing is needed I think.