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gojimmypi / VerilogLanguageExtension

Verilog Language Extension for Visual Studio
https://marketplace.visualstudio.com/items?itemName=gojimmypi.gojimmypi-verilog-language-extension
MIT License
18 stars 3 forks source link

add support for wire signed yxz; #12

Open gojimmypi opened 4 years ago

gojimmypi commented 4 years ago

per review:

Need to add support for:

wire signed yxz;

xyz ends up not being recognized as a wire.

It's the "signed" keyword that confuses it.