Closed kyletpugh closed 4 years ago
Hello @kyletpugh and thanks for taking my Verilog Language Extension for a test drive! Yes, you are correct: somehow I overlooked the gate primitives. I have the changes in the dev branch and perhaps you'd like try Version 0.3 that includes those keywords? They should all appear as LightGreen
text now.
*edit: this 0.3.0 update is now available in the Visual Studio Marketplace. Although the configuration claims it should work with Visual Studio 215, 2017, and 2019, there does not seem to be properly syntax highlighting in VS2015. VS2017 and VS2019 working fine. See https://github.com/gojimmypi/VerilogLanguageExtension/issues/7
Thank you, works great for VS2017!
Gate primitive keywords such as and, nand, or, nor, xor, xnor, not, etc, are not being highlighted. After looking through the code there does not seems to be anything written for those keywords in VerilogTokens. The wired variants, wand, wor, etc, seem to be included though. Highlighting these keywords would be nice for simple static combinational circuit modeling.