Usage of fpga DRAM in synthesis

[bala122]

Hi @tcal-x , I had a general doubt regarding synthesis of the Vexriscv core with the accelerator peripheral designed on an fpga. Are the memory resources used in synthesis restricted to flip flops, BRAM, registers, and all single cycle access elements on the fpga OR is DRAM also used by default? Do we need to write our own memory interface IPs to access DRAM/ off chip memory or is this done by default using vivado?

Essentially, I want my setup to have multi cycle memory accesses when running on an fpga, so that upon more data reuse in buffers, I see performance benefits( because I avoid these high latency accesses) Thanks, Bala.

[mithro]

Due to the fact that CFU-Playground uses LiteX (https://github.com/enjoy-digital/litex/) as the basis, it has inbuilt support for DDR using the LiteDRAM project (https://github.com/enjoy-digital/litedram) which is a low resource, fully open source memory controller and PHY which supports a wide range of FPGAs.

[bala122]

Thanks, @mithro

[tcal-x]

Hi @bala122; @aman26kbm and I were discussing a similar issue recently on Gitter, please feel free to join the conversation there.

[bala122]

Hi @tcal-x , I just wanted to know if the Vexriscv core itself utilizes the ddr memory ( already physically present in the fpga) and the controller for interfacing with it. As of now, I'm not yet concerned about the cfu unit having direct access to dram although that would be an improvement. Essentially, I wanted to know- whenever the host core( Vexriscv) synthesized on the fpga issues a load or a store command, it should take multiple cycles for access since it accesses the ddr memory( already physically present) instead of a single cycle latency element like BRAM, distributed ram or flipflops synthesized on the fpga. Thanks, Bala.

[tcal-x]

Hi @bala122 , thank you for clarifying. We delegate this part of the SoC design to Litex (the litex-boards repo specifically). If a board has external DRAM, then the SoC generated for that board will implement a DRAM controller and make the correct external connections. For example, with the Arty A7 board, this is the part of the 'platform' file: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/digilent_arty.py#L105-L134, and this is the part of the 'target' file: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/digilent_arty.py#L83-L93. Within CFU Playground, it is possible to override the default memory regions by changing arguments to the LiteX SoC initialization, but this is usually not needed.

Yes, when DRAM is used, the latency for memory loads is no longer fixed. The CPU typically has a cache, so cache hits will be low-latency, while a cache miss out to DRAM will take much longer to service.

In all cases, CFU Playground/LiteX does NOT use vendor-specific gateware IP, so we don't need to use the vendor's proprietary software. We do however instantiate device family specific primitives, for example, DDR IO cells.

[bala122]

Okay, sure. Thanks @tcal-x