OSError: Unable to find any of the cross compilation toolchains

[mamuneeb]

Hii I completed the Setup Guide Successfully, able to see the Chasing LEDs on FPGA as well as all the Golden Tests passed. But when i am executing the below command following as given here in Step 2, make prog EXTRA_LITEX_ARGS="--variant=a7-100 --sys-clk-freq 75000000" It shows /home/mamuneebcfu/CFU-Playground/scripts/pyrun /home/mamuneebcfu/CFU-Playground/proj/my_first_cfu/cfu_gen.py make -C /home/mamuneebcfu/CFU-Playground/soc -f /home/mamuneebcfu/CFU-Playground/soc/common_soc.mk prog make[1]: Entering directory '/home/mamuneebcfu/CFU-Playground/soc' Building bitstream for digilent_arty. CFU option: --cpu-cfu /home/mamuneebcfu/CFU-Playground/proj/my_first_cfu/cfu.v MAKEFLAGS=-j8 /home/mamuneebcfu/CFU-Playground/scripts/pyrun ./common_soc.py --output-dir build/digilent_arty.my_first_cfu --csr-json build/digilent_arty.my_first_cfu/csr.json --cpu-cfu /home/mamuneebcfu/CFU-Playground/proj/my_first_cfu/cfu.v --uart-baudrate 1843200 --target digilent_arty --variant=a7-100 --sys-clk-freq 75000000 --build make_soc: cpu_variant is full+cfu Variant "full+cfu" already known. INFO:S7PLL:Creating S7PLL, speedgrade -1. INFO:S7PLL:Registering Single Ended ClkIn of 100.00MHz. INFO:S7PLL:Creating ClkOut0 sys of 75.00MHz (+-10000.00ppm). INFO:S7PLL:Creating ClkOut1 eth of 25.00MHz (+-10000.00ppm). INFO:S7PLL:Creating ClkOut2 sys4x of 300.00MHz (+-10000.00ppm). INFO:S7PLL:Creating ClkOut3 sys4x_dqs of 300.00MHz (+-10000.00ppm). INFO:S7PLL:Creating ClkOut4 idelay of 200.00MHz (+-10000.00ppm). INFO:SoC: _ _
INFO:SoC: / / () /____ | |//
INFO:SoC: / // / / -)> <
INFO:SoC: /____//_/_//||
INFO:SoC: Build your hardware, easily! INFO:SoC:-------------------------------------------------------------------------------- INFO:SoC:Creating SoC... (2022-09-23 04:18:14) INFO:SoC:-------------------------------------------------------------------------------- INFO:SoC:FPGA device : xc7a100tcsg324-1. INFO:SoC:System clock: 75.000MHz. INFO:SoCBusHandler:Creating Bus Handler... INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space. INFO:SoCBusHandler:Adding reserved Bus Regions... INFO:SoCBusHandler:Bus Handler created. INFO:SoCCSRHandler:Creating CSR Handler... INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations). INFO:SoCCSRHandler:Adding reserved CSRs... INFO:SoCCSRHandler:CSR Handler created. INFO:SoCIRQHandler:Creating IRQ Handler... INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations). INFO:SoCIRQHandler:Adding reserved IRQs... INFO:SoCIRQHandler:IRQ Handler created. INFO:SoC:-------------------------------------------------------------------------------- INFO:SoC:Initial SoC: INFO:SoC:-------------------------------------------------------------------------------- INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space. INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations). INFO:SoC:IRQ Handler (up to 32 Locations). INFO:SoC:-------------------------------------------------------------------------------- INFO:SoC:Controller ctrl added. INFO:SoC:CPU vexriscv added. INFO:SoC:CPU vexriscv adding IO Region 0 at 0x80000000 (Size: 0x80000000). INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False. INFO:SoC:CPU vexriscv overriding sram mapping from 0x01000000 to 0x10000000. INFO:SoC:CPU vexriscv setting reset address to 0x00000000. INFO:SoC:CPU vexriscv adding Bus Master(s). INFO:SoCBusHandler:cpu_bus0 added as Bus Master. INFO:SoCBusHandler:cpu_bus1 added as Bus Master. INFO:SoC:CPU vexriscv adding Interrupt(s). INFO:SoC:CPU vexriscv adding SoC components. INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00020000, Mode: R, Cached: True Linker: False. INFO:SoCBusHandler:rom added as Bus Slave. INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00020000, Mode: R, Cached: True Linker: False. INFO:SoCBusHandler:sram Region added at Origin: 0x10000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False. INFO:SoCBusHandler:sram added as Bus Slave. INFO:SoC:RAM sram added Origin: 0x10000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False. INFO:SoCIRQHandler:uart IRQ allocated at Location 0. INFO:SoCIRQHandler:timer0 IRQ allocated at Location 1. INFO:SoCBusHandler:main_ram Region added at Origin: 0x40000000, Size: 0x10000000, Mode: RW, Cached: True Linker: False. INFO:SoCBusHandler:main_ram added as Bus Slave. INFO:SoC:CSR Bridge csr added. INFO:SoCBusHandler:csr Region added at Origin: 0xf0000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False. INFO:SoCBusHandler:csr added as Bus Slave. INFO:SoCCSRHandler:csr added as CSR Master. INFO:SoCBusHandler:Interconnect: InterconnectShared (2 <-> 4). INFO:SoCCSRHandler:ctrl CSR allocated at Location 0. INFO:SoCCSRHandler:ddrphy CSR allocated at Location 1. INFO:SoCCSRHandler:identifier_mem CSR allocated at Location 2. INFO:SoCCSRHandler:leds CSR allocated at Location 3. INFO:SoCCSRHandler:sdram CSR allocated at Location 4. INFO:SoCCSRHandler:timer0 CSR allocated at Location 5. INFO:SoCCSRHandler:uart CSR allocated at Location 6. INFO:SoC:-------------------------------------------------------------------------------- INFO:SoC:Finalized SoC: INFO:SoC:-------------------------------------------------------------------------------- INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space. IO Regions: (1) io0 : Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False Bus Regions: (4) rom : Origin: 0x00000000, Size: 0x00020000, Mode: R, Cached: True Linker: False sram : Origin: 0x10000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False main_ram : Origin: 0x40000000, Size: 0x10000000, Mode: RW, Cached: True Linker: False csr : Origin: 0xf0000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False Bus Masters: (2)

• cpu_bus0
• cpu_bus1 Bus Slaves: (4)
• rom
• sram
• main_ram
• csr INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations). CSR Locations: (7)
• ctrl : 0
• ddrphy : 1
• identifier_mem : 2
• leds : 3
• sdram : 4
• timer0 : 5
• uart : 6 INFO:SoC:IRQ Handler (up to 32 Locations). IRQ Locations: (2)
• uart : 0
• timer0 : 1 INFO:SoC:-------------------------------------------------------------------------------- INFO:S7PLL:Config: divclk_divide : 1 clkout1_freq : 25.00MHz clkout1_divide: 48 clkout1_phase : 0.00° clkout4_freq : 200.00MHz clkout4_divide: 6 clkout4_phase : 0.00° clkout0_freq : 75.00MHz clkout0_divide: 16 clkout0_phase : 0.00° clkout2_freq : 300.00MHz clkout2_divide: 4 clkout2_phase : 0.00° clkout3_freq : 300.00MHz clkout3_divide: 4 clkout3_phase : 90.00° vco : 1200.00MHz clkfbout_mult : 12 Traceback (most recent call last): File "./common_soc.py", line 57, in main() File "./common_soc.py", line 53, in main workflow.run() File "/home/mamuneebcfu/CFU-Playground/soc/board_specific_workflows/general.py", line 125, in run soc_builder = self.build_soc(soc) File "/home/mamuneebcfu/CFU-Playground/soc/board_specific_workflows/digilent_arty.py", line 73, in build_soc return super().build_soc(soc, kwargs) File "/home/mamuneebcfu/CFU-Playground/soc/board_specific_workflows/general.py", line 102, in build_soc soc_builder.build(run=self.args.build, kwargs) File "/home/mamuneebcfu/CFU-Playground/third_party/python/litex/litex/soc/integration/builder.py", line 325, in build self._generate_includes(with_bios=with_bios) File "/home/mamuneebcfu/CFU-Playground/third_party/python/litex/litex/soc/integration/builder.py", line 180, in _generate_includes variables_contents = self._get_variables_contents() File "/home/mamuneebcfu/CFU-Playground/third_party/python/litex/litex/soc/integration/builder.py", line 149, in _get_variables_contents for k, v in export.get_cpu_mak(self.soc.cpu, self.compile_software): File "/home/mamuneebcfu/CFU-Playground/third_party/python/litex/litex/soc/integration/export.py", line 92, in get_cpu_mak selected_triple = select_triple(triple) File "/home/mamuneebcfu/CFU-Playground/third_party/python/litex/litex/soc/integration/export.py", line 90, in select_triple raise OSError(msg) OSError: Unable to find any of the cross compilation toolchains:
• riscv64-pc-linux-musl
• riscv64-unknown-elf
• riscv64-unknown-linux-gnu
• riscv64-elf
• riscv64-linux
• riscv64-linux-gnu
• riscv-sifive-elf
• riscv64-none-elf
• riscv32-unknown-elf
• riscv32-unknown-linux-gnu
• riscv32-elf
• riscv-none-embed
• riscv-none-elf

make[1]: [/home/mamuneebcfu/CFU-Playground/soc/common_soc.mk:115: build/digilent_arty.my_first_cfu/gateware/digilent_arty.bit] Error 1 make[1]: Leaving directory '/home/mamuneebcfu/CFU-Playground/soc' make: [../proj.mk:312: prog] Error 2

Please help me with this.

[tcal-x]

Did you check if the riscv32 tools are in your path? Type "riscv32" then TAB two or three times to get name completion -- it should either show many options, or nothing. If nothing, then perhaps you exited the Conda environment accidentally without realizing it. You need to be in the Conda environment to access these tools -- in this case since you're using Symbiflow, type make enter-sf to enter or re-enter the Conda env.

[mamuneeb]

Hii Thanks a lot @tcal-x , i had accidently exited the Conda environment. The issue is resolved. Thank you.