Closed antonblanchard closed 2 years ago
I fixed it one way. Let's see how robust this is. Turns None
Signals into new floating nets so that instantiations can proceed and Spice can be happy:
** SPICE netlist generated by bigspicy.py at Tue Sep 6 02:39:55 2022 UTC
.SUBCKT test
+ VGND VPWR hi
** [instance const_hi of sky130_fd_sc_hd__conb_1, params={} connections=['VGND: [connection const_hi/VGND =>[signal: VGND w=1]]', 'VNB: [connection const_hi/VNB =>[signal: VGND w=1]]', 'VPB: [connection const_hi/VPB =>[signal: VPWR w=1]]', 'VPWR: [connection const_hi/VPWR =>[signal: VPWR w=1]]', 'HI: [connection const_hi/HI =>[signal: hi w=1]]']]
const_hi VGND VGND VPWR VPWR hi no_conn_0 sky130_fd_sc_hd__conb_1
.ENDS
When trying to import some sky130 gate level verilog, bigspicy fails with:
The problem is a tie cell, in which a disconnected pin is expected (both LO and HI are rarely used together). A verilog test case:
And the spice:
run with: