Improve transistor definitions in xschem lvs export

[StefanSchippers]

• strip unusted parameters on LVS export
• avoids X prefix

• fix substrate pin of vnpn_10x10.sym (was named "B" instead of "S")

  (Still to be decided if we want to make similar changes for LVS on other devices (moscap and others)

Fixes #101

[proppy]

/cc @atorkmabrains FYI

[atorkmabrains]

@StefanSchippers Could you please make sure to add a similar PR on: https://github.com/efabless/globalfoundries-pdk-libs-gf180mcu_fd_pr

[proppy]

@StefanSchippers Could you please make sure to add a similar PR on: https://github.com/efabless/globalfoundries-pdk-libs-gf180mcu_fd_pr

Done here: https://github.com/efabless/globalfoundries-pdk-libs-gf180mcu_fd_pr/pull/23

[proppy]

@StefanSchippers can lvs_format also be used to other component used only by simulation from the LVS netlist? (C blocks for lab pin, spice model, etc)

[StefanSchippers]

If you add an lvs_format this takes precedence over format when doing LVS netlists. This can be used to exclude simulation-only devices from LVS netlist, like for example in: lvs_format="* @name @pinlist @value" Notice the '*' at the beginning. This will add just a commented line in the netlist. Just make sure lvs_format is not empty, because in this case the xschem netlister will revert to format attribute. Even a single space will be ok, like in: lvs_format=" "

[proppy]

Just make sure lvs_format is not empty, because in this case the xschem netlister will revert to format attribute. Even a single space will be ok, like in: lvs_format=" "

Yes, I went for lvs_format="*" :) Thanks for the tip!