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Understand and mitigate software-observable side-channels
BSD 3-Clause "New" or "Revised" License
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Create a header just for page + cache line sizes #118

Closed mmdriley closed 4 years ago

mmdriley commented 4 years ago

Break these out of instr.h, which comes with a lot of other stuff.

Remove some other redundant definitions that were mostly unused.

asteinha commented 4 years ago

Basically I just don't want to introduce a false negative on PPC64 and I don't know what the cache line sector means. That should be clarified before we increase the cache line size for PPC64. Otherwise LGTM.

mmdriley commented 4 years ago

Yeah, that confused me too.

There are no mentions of "sectors" in the POWER ISA manual, but reading through the POWER9 User's Manual it seems like sectors are a technique for allowing instructions to proceed once the half of the cache line they cared about was loaded. See in particular:

Support for up to eight outstanding L1 cache-line misses with critical data forwarding; critical sector first.

and

Each core contains a 32 KB, 8-way set-associative L1 instruction cache (I-cache). The I-cache is allocated in 128-byte lines with 32-byte sector valid tracking.

This makes some sense since DDR3+ RAM transfers in bursts of 64 bytes (matching the cache line size more commonly seen elsewhere)

FWIW, here are the corresponding definitions in Abseil, which show 128-byte cache lines on ppc64: https://github.com/abseil/abseil-cpp/blob/078b89b3c046d230ef3ad39494e5852184eb528b/absl/base/optimization.h#L71-L91