Open tangxifan opened 3 years ago
The behavioral/functional Verilog netlists should work in HDL simulation
The behavioral Verilog netlist of High-Density standard cell stdfrtp has critical bugs which causes HDL simulation fails. A quick example:
stdfrtp
https://cs.opensource.google/skywater-pdk/skywater-pdk/+/master:libraries/sky130_fd_sc_hd/latest/cells/sdfrtp/sky130_fd_sc_hd__sdfrtp.behavioral.v;l=80
**Same problem may happen to other flip-flop netlists``
You can see the nets D_delayed, SCD_delayed and CLK_delayed are undriven nets which are denoted as X signals in HDL simulations. As a result, the flip-flop Verilog netlist is malfunctional.
D_delayed
SCD_delayed
CLK_delayed
X
@mithro,
I had the same issue as explained above by @tangxifan.
Expected Behavior
The behavioral/functional Verilog netlists should work in HDL simulation
Actual Behavior
The behavioral Verilog netlist of High-Density standard cell
stdfrtp
has critical bugs which causes HDL simulation fails. A quick example:**Same problem may happen to other flip-flop netlists``
You can see the nets
D_delayed
,SCD_delayed
andCLK_delayed
are undriven nets which are denoted asX
signals in HDL simulations. As a result, the flip-flop Verilog netlist is malfunctional.Steps to Reproduce the Problem
Specifications