google / skywater-pdk

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
https://skywater-pdk.rtfd.io
Apache License 2.0
2.99k stars 391 forks source link

gate-level simulation using skywater and modelsim #404

Open zliu1Charlotte opened 2 years ago

zliu1Charlotte commented 2 years ago

Dear all, I loaded my post-syn netlist, .sdf, testbench, and skywater cells using modelsim command line. but it seems like my gate-level simulation's inputs and outputs are all remained as x. and it shows no errors. It seems like none of the skywater cells are actived and such? I looked into each cells, and I see that for example a inv, and its input and output are both x. I feel like I am not loading them correctly in vsim? btw rtl-level simulation using vsim worked as expected. vsim complains about the wire type so I changed all the needed cells to wire instead of none. But I do not know why all inputs and outputs remained x. Let me know if you have seem this before. if you need any files i can provide them thanks.