VCS error due to defining default net type as none for primitives

[M0stafaRady]

Expected Behavior

VCS compile the library Verilog files

Actual Behavior

VCS throws errors like this for primitives

Identifier 'SET' has not been declared yet. If this error is not expected, 
  please check if you have set default_nettype to none. 

line 46

This error shows only with primitives. Compilation passed after commenting out the default_nettype none line before primitives.

Steps to Reproduce the Problem

1. compile the primitives with VCS

Specifications

• Version: T-2022.06_Full64
• Platform: Chronologic VCS (TM)

[amm-efabless]

Is it safe to comment out `default_nettype none and why does this help? I'm guessing it's a VCS quirk. I'm also not sure why SET is flagged but other ports/identifiers are not. SET seems to be declared as one would expect, but maybe this is a VCS bug or some other issue to do with SET often being a keyword in various implementations...?

[M0stafaRady]

It works because the default net type in verilog is wire. So if the default net type doesn't change any net with no definition would considered as a wire. The 2 code below would be equivalent:

    input  SET  ;

    input  wire SET  ;

but they are not in the case of default net type none

[amm-efabless]

Ah right, thanks @M0stafaRady! So I assume the reason it isn't flagged on the line above it (output Q) is because later Q is declared as a reg. Cool, thanks for the feedback.