search

google / skywater-pdk

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
https://skywater-pdk.rtfd.io
Apache License 2.0
3k stars 391 forks source link

Access to pg_pins' timing lib #435

Open leolin1206 opened 4 months ago

leolin1206 commented 4 months ago

Hello,

I hope you are doing well.

I tried to access the timing library for the pg_pins but I wasn't able to find any information from the libraries. I was able to find specific input/output pin timing info but not the general pg_pin timing info. Does anyone know any access to the timing info for pg_pin timings?

pg_pin ("VGND") { pg_type : "primary_ground"; related_bias_pin : "VPB"; voltage_name : "VGND"; } pg_pin ("VNB") { pg_type : "nwell"; physical_connection : "device_layer"; voltage_name : "VNB"; } pg_pin ("VPB") { pg_type : "pwell"; physical_connection : "device_layer"; voltage_name : "VPB"; } pg_pin ("VPWR") { pg_type : "primary_power"; related_bias_pin : "VNB"; voltage_name : "VPWR"; }

Thank you very much for your assists and directions.

Leo

rovinski commented 4 months ago

The Liberty timing model does not support timings on pg_pins. What is your use case for this? Generally this kind of information would never be needed in a digital flow.