Actually run the test bench, record values into output VCD file and render them with wavedrom in documentation

[mithro]

The PDK currently has auto-generated "test" benches for all the standard cells and models. See the following examples;

• https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hd/+/refs/heads/master/cells/a2111o/sky130_fd_sc_hd__a2111o.tb.v
• https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hd/+/refs/heads/master/cells/sdfbbn/sky130_fd_sc_hd__sdfbbn.tb.v

It would be good to take these test benches, run them through the simulator and saved the output to VCD files. Any open source simulator like Verilator or Icarus Verilog could be used for this.

Once there are VCD files, these should then be rendered with wavedrom to give nice waveform diagrams in the documentation on ReadTheDocs. This could use be done with one of the wavedrom Sphinx plugins.

[kkiningh]

I don't think you can use Verilator for this without changing the test benches since Verilator doesn't support simulating delays (e.g. line 110 here).

[mithro]

@kkiningh - If I recall correctly, support as added recently?

[kkiningh]

In the FAQ it says "All delays (#) are ignored, as they are in synthesis." Maybe the documentation hasn't been updated?

[mithro]

If I'm correct, it would have probably only been in the last few months as Verilator pushes forward supporting more SystemVerilog and UVM stuff.

[kkiningh]

I get the following error running with the current Verilator HEAD (84b83079).

%Warning-STMTDLY: test.v:29:10: Unsupported: Ignoring delay on this delayed statement.
                              : ... In instance top
   29 |         #20   A1   = 1'b0;
      |          ^~
                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.

EDIT: Icarus doesn't seem to complain, maybe that's the best option here.

[mithro]

Guess I'm wrong. Let's start with Icarus first then?