This is too generic and often we would like to specify the options differently (ex. loop-back channels should not be flopped) while X output channel should have a fifo depth of 5, and Z output channel should have a fifo depth of 4.
Current best alternative workaround (limit 100 words)
Right now, the option is to have no I/O options and insert the additional options manually in Verilog.
Your view of the "best case XLS enhancement" (limit 100 words)
Two options are considered
Enhance DSLX to support tags/configurations on each channel. (ex. this channel should have fifo depth of 5, or this channel should have no flops added).
Enhance codegen options to specify options per-channel.
This would be extremely useful together with the recently added multi-proc codegen.
The IO settings could be provided, for example as a proto file, as it is done for RAM configuration in opt_main
What's hard to do? (limit 100 words)
Currently I/O options for channels are global and specified as side-band options. https://google.github.io/xls/codegen_options
This is too generic and often we would like to specify the options differently (ex. loop-back channels should not be flopped) while X output channel should have a fifo depth of 5, and Z output channel should have a fifo depth of 4.
Current best alternative workaround (limit 100 words)
Right now, the option is to have no I/O options and insert the additional options manually in Verilog.
Your view of the "best case XLS enhancement" (limit 100 words)
Two options are considered