Closed rw1nkler closed 2 months ago
I'm not able to reproduce this error w/ v0.0.0-5199-gf59b8a886: https://colab.research.google.com/gist/proppy/b63996aeb0dcbcca7a8271fc322e85c2/xls-playground-sandbox.ipynb
can you confirm which build are you using?
You can observe the problem using the current main. I pushed the code here. Here is the rule that can be used to spot the problem:
bazel build //xls/examples:passthrough_nested_opt_ir
@proppy
This issue occurs in https://github.com/google/xls/pull/1315 as well.
One interesting thing is that we still get errors from the inlining pass even after disabling it in the build rules through "inline_procs": "false"
in opt_ir_args
(see the CI log). It looks like there is a place in the IR optimization process that includes the inlining pass without checking for the value of the inline_procs
flag.
It looks like it might be done here. CreateOptimizationPassPipeline
adds the UnrollingAndInliningPassGroup to the optimization passes.
@lpawelcz assuming this is blocking #1211 ?
It looks like there is a place in the IR optimization process that includes the inlining pass without checking for the value of the inline_procs flag
It seems you currently have to remove the flag from opt_ir_args
(and not set it to false) in order to disable inlining from a xls_ir_opt_ir
target. The handling of this attr in the bzl macro seems lossy, filed #1464.
@lpawelcz assuming this is blocking #1211 ?
@proppy Yes, this is a blocker for the work on ZSTD decoder because we are not able to generate correct verilog code for the modules and run place and route flows.
@hongted it seems that the problem still exists. I updated the example that shows the problem: https://github.com/antmicro/xls/blob/d3ee4f64e4935f939fe096e0d47c6e446474f28e/xls/examples/passthrough.x
@grebe @hongted is there a workaround for this? @rw1nkler is understanding is that inlining is needed for RAM usage.
In order to unblock verilog and PD: I was thinking that they may be able to codegen the memory interface w/o inlining as a regular DSLX proc w/ a channel rdv/vld (without any DSLX ram integration) and stub out the verilog module w/ an adapter to the ram macros; wdyt?
@grebe @hongted is there a workaround for this? @rw1nkler is understanding is that inlining is needed for RAM usage.
The problem is quite specific. So in some cases it is easier to split interaction with RAM between two child processes - one responsible for writing data to RAM, and one for reading if from the memory. In that case we cannot generate a complete Verilog with proper RAM signals, because only half of the interface is available for each child process and the RAM rewriting mechanism will fail. In this particular scenario it is required to inline the proc and allow for rewriting all signal at once. I'm not sure but inlining can also affect the scheduler in that case.
I believe this is a bug introduced with the new token semantics; the inliner wasn't handling that appropriately. I think I have a fix forthcoming!
It works! Thank you @ericastor
Describe the bug
Inlining a proc that spawns another proc and contains a logic that performs operations on tokens, causes an internal error.
To Reproduce
One can use the following DSLX code to observe the issue:
Here is a bazel rule that can be used to observe the problem:
Building the
passthrough_nested_opt_ir
target causes the following error:What is interesting, a procs with empty
next()
, like the one below, can be inlined without any problems:Expected behavior
It should be possible to inline the procs