Run generated verilog through verilog formatter

[meheff]

Verible verilog formatter would probably do the trick:

https://google.github.io/verible/verilog_format.html

Likely invocation:

verible-verilog-format /tmp/foo.v --try_wrap_long_lines

[meheff]

@taktoa This will cause a wrinkle in Verilog line tracking. I think it can be handled by analyzing the preformatted and postformatted Verilog and mutating the LineInfo accordingly. I imagine the formatter is just adding/removing white space.

[hzeller]

Verible would break up very long lines to be shorter. In which way is the line information used ? Is it passed in a side-channel to tools that consume the generated verilog ?