XLS generates invalid multidimensional array access in Verilog-only mode

[meheff]

For multi-dimensional arrays, XLS generates Verilog which looks like:

  wire [36:0] x16[0:0][0:8];
  assign x16[0] = x4_unflattened[x10 > 42'h000_0000_000b ? 42'h000_0000_000b : x10 + 42'h000_0000_0000];

iverilog is unhappy with this and emits an error:

error: Array x16['sd0] needs 2 indices, but got only 1. (net)

Switching to packed arrays would resolve this issue: https://github.com/google/xls/issues/320

[meheff]

Looks like this is invalid Verilog as other simulator reject the construct in non-SystemVerilog mode. Looks lke the problematic IR node may be array slice.