goossens-springer
commented
3 weeks ago The good correction is to remove the intermediate "nbi" variable and directly compute on the nb_instruction argument:
void fetching_decoding_ip( unsigned int start_pc, unsigned int code_ram[CODE_RAM_SIZE], unsigned int *nb_instruction){
pragma HLS INTERFACE s_axilite port=start_pc
pragma HLS INTERFACE s_axilite port=code_ram
pragma HLS INTERFACE s_axilite port=nb_instruction
pragma HLS INTERFACE s_axilite port=return
code_address_t pc; instruction_t instruction; bit_t is_running; decoded_instruction_t d_i; pc = start_pc; *nb_instruction = 0; do{
pragma HLS PIPELINE II=3
fetch(pc, code_ram, &instruction);
decode(instruction, &d_i);
execute(pc, d_i, &pc);
statistic_update(nb_instruction);
running_cond_update(instruction, &is_running);} while (is_running); }
Probably there is an undesirable optimisation of the synthesizer (set the nb_instruction value with the first iteration nbi value instead of the last iteration one).
bg.
atreistm
cento
I am using Vivado and Vitis 2024 with an Arty Z7-20 board.
When I run the second or third steps of the single cycle implementation, I get 1 fetched and decoded instructions instead of 14. I saw one suggestion to make nbi a static (in the Vitis application?) but it did not help.
When I run a C-Simulation , the Vitis HLS project prints properly.
Any ideas?