this function has floating point code interlaced to optimize for the pentium fpu pipeline, with fxch instructions which are free on the pentium and alleviate pipeline stalls resulting in faster operation.
on nearly any other processor this serves no function except to take additional cycles to do the same operation. rewrite this function to avoid the use of fxch instructions - every fxch removed is 4 cycles saved on a 486.
this function has floating point code interlaced to optimize for the pentium fpu pipeline, with fxch instructions which are free on the pentium and alleviate pipeline stalls resulting in faster operation.
on nearly any other processor this serves no function except to take additional cycles to do the same operation. rewrite this function to avoid the use of fxch instructions - every fxch removed is 4 cycles saved on a 486.