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gpanders / vitis_example

Example project for Xilinx Vitis
MIT License
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ERROR: [Common 17-70] Application Exception: Need an implemented design open to write bitstream #1

Open jrjbertram opened 4 years ago

jrjbertram commented 4 years ago

Hello,

Ran into the same issue you were having when you created this repo. Tried out your repo to see if it might happen to work for me and ran into this issue.

ERROR: [Common 17-70] Application Exception: Need an implemented design open to write bitstream

Larger error log somewhat before that error occurred:

# save_bd_design
Wrote  : </home/adclab/vitis_example/build/bd/vitis_example.srcs/sources_1/bd/vitis_example/vitis_example.bd> 
# validate_bd_design
INFO: [PSU-1]  DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change 
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_0 clk_wiz propagate
# set bd_file $build_dir/bd/$design_name.srcs/sources_1/bd/$design_name/$design_name.bd
# generate_target all [get_files $bd_file]
INFO: [BD 41-1662] The design 'vitis_example.bd' is already validated. Therefore parameter propagation will not be re-run.
Wrote  : </home/adclab/vitis_example/build/bd/vitis_example.srcs/sources_1/bd/vitis_example/vitis_example.bd> 
VHDL Output written to : /home/adclab/vitis_example/build/bd/vitis_example.srcs/sources_1/bd/vitis_example/synth/vitis_example.v
VHDL Output written to : /home/adclab/vitis_example/build/bd/vitis_example.srcs/sources_1/bd/vitis_example/sim/vitis_example.v
VHDL Output written to : /home/adclab/vitis_example/build/bd/vitis_example.srcs/sources_1/bd/vitis_example/hdl/vitis_example_wrapper.v
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_wiz_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_3 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_4 .
INFO: [xilinx.com:ip:zynq_ultra_ps_e:3.3-0] vitis_example_zynq_ultra_ps_e_0_0: 
Changes in your design (including the PCW configuration settings) are not automatically exported from Vivado to Xilinx's SDK, Petalinux or Yocto.
This is by design to avoid disrupting existing embedded development efforts. To have any changes of your design taking effect in the embedded software flow please export your
design by going through Vivado's main menu, click on File, then Export finally select Export Hardware, please ensure you click on the Include BitStream option.
The auto-generated HDF file is all you need to import in Xilinx's SDK, Petalinux or Yocto for your changes to be reflected in the Embedded Software Flow.
For more information, please consult PG201, section: Exporting PCW Settings to Embedded Software Flows
INFO: [PSU-0] Address Range of DDR (0x7ff00000 to 0x7fffffff) is reserved by PMU for internal purpose.
INFO: [BD 41-1029] Generation completed for the IP Integrator block zynq_ultra_ps_e_0 .
Exporting to file /home/adclab/vitis_example/build/bd/vitis_example.srcs/sources_1/bd/vitis_example/hw_handoff/vitis_example.hwh
Generated Block Design Tcl file /home/adclab/vitis_example/build/bd/vitis_example.srcs/sources_1/bd/vitis_example/hw_handoff/vitis_example_bd.tcl
Generated Hardware Definition File /home/adclab/vitis_example/build/bd/vitis_example.srcs/sources_1/bd/vitis_example/synth/vitis_example.hwdef
generate_target: Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 2915.613 ; gain = 142.344 ; free physical = 14700 ; free virtual = 57976
# set_property pfm_name $design_name [get_files $bd_file]
# set_property generate_synth_checkpoint true [get_files $bd_file]
# make_wrapper -top -import [get_files $bd_file]
WARNING: [Vivado 12-3482] The generated wrapper file has already been imported into the project, the imported file is:
'/home/adclab/vitis_example/build/bd/vitis_example.srcs/sources_1/imports/hdl/vitis_example_wrapper.v'
# update_compile_order -fileset sources_1
# update_compile_order -fileset sim_1
# launch_runs impl_1 -to_step write_bitstream -jobs $num_threads
[Tue Jul 14 14:12:58 2020] Launched vitis_example_proc_sys_reset_4_0_synth_1, vitis_example_proc_sys_reset_3_0_synth_1, vitis_example_proc_sys_reset_2_0_synth_1, vitis_example_proc_sys_reset_0_0_synth_1, vitis_example_proc_sys_reset_1_0_synth_1, vitis_example_clk_wiz_0_0_synth_1, vitis_example_zynq_ultra_ps_e_0_0_synth_1, synth_1...
Run output will be captured here:
vitis_example_proc_sys_reset_4_0_synth_1: /home/adclab/vitis_example/build/bd/vitis_example.runs/vitis_example_proc_sys_reset_4_0_synth_1/runme.log
vitis_example_proc_sys_reset_3_0_synth_1: /home/adclab/vitis_example/build/bd/vitis_example.runs/vitis_example_proc_sys_reset_3_0_synth_1/runme.log
vitis_example_proc_sys_reset_2_0_synth_1: /home/adclab/vitis_example/build/bd/vitis_example.runs/vitis_example_proc_sys_reset_2_0_synth_1/runme.log
vitis_example_proc_sys_reset_0_0_synth_1: /home/adclab/vitis_example/build/bd/vitis_example.runs/vitis_example_proc_sys_reset_0_0_synth_1/runme.log
vitis_example_proc_sys_reset_1_0_synth_1: /home/adclab/vitis_example/build/bd/vitis_example.runs/vitis_example_proc_sys_reset_1_0_synth_1/runme.log
vitis_example_clk_wiz_0_0_synth_1: /home/adclab/vitis_example/build/bd/vitis_example.runs/vitis_example_clk_wiz_0_0_synth_1/runme.log
vitis_example_zynq_ultra_ps_e_0_0_synth_1: /home/adclab/vitis_example/build/bd/vitis_example.runs/vitis_example_zynq_ultra_ps_e_0_0_synth_1/runme.log
synth_1: /home/adclab/vitis_example/build/bd/vitis_example.runs/synth_1/runme.log
[Tue Jul 14 14:12:58 2020] Launched impl_1...
Run output will be captured here: /home/adclab/vitis_example/build/bd/vitis_example.runs/impl_1/runme.log
# wait_on_run impl_1
[Tue Jul 14 14:12:58 2020] Waiting for impl_1 to finish...
[Tue Jul 14 14:13:14 2020] impl_1 finished
WARNING: [Vivado 12-8222] Failed run(s) : 'vitis_example_proc_sys_reset_4_0_synth_1', 'vitis_example_proc_sys_reset_3_0_synth_1', 'vitis_example_proc_sys_reset_2_0_synth_1', 'vitis_example_proc_sys_reset_0_0_synth_1', 'vitis_example_proc_sys_reset_1_0_synth_1', 'vitis_example_clk_wiz_0_0_synth_1', 'vitis_example_zynq_ultra_ps_e_0_0_synth_1'
wait_on_run: Time (s): cpu = 00:01:25 ; elapsed = 00:00:15 . Memory (MB): peak = 3075.688 ; gain = 0.000 ; free physical = 14661 ; free virtual = 57938
# set_property platform.default_output_type "sd_card" [current_project]
# set_property platform.design_intent.embedded "true" [current_project]
# set_property platform.design_intent.server_managed "false" [current_project]
# set_property platform.design_intent.external_host "false" [current_project]
# set_property platform.design_intent.datacenter "false" [current_project]
# write_hw_platform -force -include_bit build/$design_name.xsa
INFO: [Vivado 12-4895] Creating Hardware Platform: build/vitis_example.xsa ...
INFO: [Hsi 55-2053] elapsed time for repository (/tools/Xilinx/Vivado/2020.1/data/embeddedsw) loading 0 seconds
INFO: [Project 1-1042] Successfully generated hpfm file
ERROR: [Common 17-70] Application Exception: Need an implemented design open to write bitstream. Aborting write_hw_platform..
Vivado%

I'm probably missing a simple step somewhere. If I figure out what went wrong I'll post an update here. Capturing in case others run into this in the future.

gpanders commented 4 years ago

It looks like this is happening because the implementation step failed:

WARNING: [Vivado 12-8222] Failed run(s) : 'vitis_example_proc_sys_reset_4_0_synth_1', 'vitis_example_proc_sys_reset_3_0_synth_1', 'vitis_example_proc_sys_reset_2_0_synth_1', 'vitis_example_proc_sys_reset_0_0_synth_1', 'vitis_example_proc_sys_reset_1_0_synth_1', 'vitis_example_clk_wiz_0_0_synth_1', 'vitis_example_zynq_ultra_ps_e_0_0_synth_1

Can you take a look at the log files for these IP and see if you spot any obvious errors?

jrjbertram commented 4 years ago

Not finding any log files. Maybe there's an implied build step within vivado that I'm not performing that's so obvious it's not in the instructions you list, perhaps? Could be I've missed some other simple step somewhere too.

Here's a list of files under the build directory. I don't even have the *.runs directory after building. 

(base) adclab@solo:~/vitis_example/build/bd$ ls -lr
total 32
-rw-r--r-- 1 adclab adclab 9527 Jul 14 14:14 vitis_example.xpr
drwxr-xr-x 3 adclab adclab 4096 Jul 15 16:01 vitis_example.srcs
drwxr-xr-x 2 adclab adclab 4096 Jul 15 16:01 vitis_example.ip_user_files
drwxr-xr-x 2 adclab adclab 4096 Jul 15 16:01 vitis_example.hw
drwxr-xr-x 3 adclab adclab 4096 Jul 15 16:01 vitis_example.hbs
drwxr-xr-x 3 adclab adclab 4096 Jul 15 16:01 vitis_example.cache
(base) adclab@solo:~/vitis_example/build/bd$ ls -lR
.:
total 32
drwxr-xr-x 3 adclab adclab 4096 Jul 15 16:01 vitis_example.cache
drwxr-xr-x 3 adclab adclab 4096 Jul 15 16:01 vitis_example.hbs
drwxr-xr-x 2 adclab adclab 4096 Jul 15 16:01 vitis_example.hw
drwxr-xr-x 2 adclab adclab 4096 Jul 15 16:01 vitis_example.ip_user_files
drwxr-xr-x 3 adclab adclab 4096 Jul 15 16:01 vitis_example.srcs
-rw-r--r-- 1 adclab adclab 9527 Jul 14 14:14 vitis_example.xpr

./vitis_example.cache:
total 4
drwxr-xr-x 2 adclab adclab 4096 Jul 14 14:14 wt

./vitis_example.cache/wt:
total 4
-rw-r--r-- 1 adclab adclab 58 Jul 14 14:14 project.wpc

./vitis_example.hbs:
total 4
drwxr-xr-x 2 adclab adclab 4096 Jul 14 14:14 hier

./vitis_example.hbs/hier:
total 0

./vitis_example.hw:
total 4
-rw-r--r-- 1 adclab adclab 284 Jul 14 14:14 vitis_example.lpr

./vitis_example.ip_user_files:
total 0

./vitis_example.srcs:
total 4
drwxr-xr-x 3 adclab adclab 4096 Jul 14 14:14 sources_1

./vitis_example.srcs/sources_1:
total 4
drwxr-xr-x 3 adclab adclab 4096 Jul 14 14:14 bd

./vitis_example.srcs/sources_1/bd:
total 4
drwxr-xr-x 2 adclab adclab 4096 Jul 14 14:14 vitis_example

./vitis_example.srcs/sources_1/bd/vitis_example:
total 4
-rw-r--r-- 1 adclab adclab 245 Jul 14 14:14 vitis_example.bd
gpanders commented 4 years ago

Maybe there's an implied build step within vivado that I'm not performing that's so obvious it's not in the instructions you list, perhaps? Could be I've missed some other simple step somewhere too.

I don't think so. For some reason Vivado is failing without giving any useful error messages. The fact that it's not even creating the .runs directory is really suspicious.. Are you able to build other Vivado designs on this same machine?

Also, you may be able to skip this step entirely. Unless you have some custom logic in your design that you need included, you can just download a pre-packaged platform file from Xilinx's website. You will also need to modify the Makefile a bit so that the build system no longer tries to build the platform manually. But this lets you skip the entire Vivado step and move directly on to writing the kernels and host OpenCL code.