gpgpu-sim / gpgpu-sim_distribution

GPGPU-Sim provides a detailed simulation model of contemporary NVIDIA GPUs running CUDA and/or OpenCL workloads. It includes support for features such as TensorCores and CUDA Dynamic Parallelism as well as a performance visualization tool, AerialVisoin, and an integrated energy model, GPUWattch.
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How to turn off terminal ouput? #170

Open KMFtcy opened 4 years ago

KMFtcy commented 4 years ago

While I'm running a cuda application on gpgpu-sim, there will be lots of gpu status pumped out. ` GPGPU-Sim Simulator Version 4.0.0 [build gpgpu-sim_git-commit-e7fbfaa347c0acf8a6702c1e684a8e2ad8d3f733_modified_0]

GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable: 1=functional simulation only, 0=detailed performance simulator) GPGPU-Sim PTX: overriding embedded ptx with ptx file (PTX_SIM_USE_PTX_FILE is set) GPGPU-Sim: Configuration options:

-save_embedded_ptx 0 # saves ptx files embedded in binary as .ptx -keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs -gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file -gpgpu_occupancy_sm_number 20 # The SM number to pass to ptxas when getting register usage for computing GPU occupancy. This parameter is required in the config. -ptx_opcode_latency_int 4,13,4,5,145,32 # Opcode latencies for integers <ADD,MAX,MUL,MAD,DIV,SHFL>Default 1,1,19,25,145,32 -ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points <ADD,MAX,MUL,MAD,DIV>Default 1,1,1,1,30 -ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points <ADD,MAX,MUL,MAD,DIV>Default 8,8,8,8,335 -ptx_opcode_latency_sfu 8 # Opcode latencies for SFU instructionsDefault 8 -ptx_opcode_latency_tesnor 64 # Opcode latencies for Tensor instructionsDefault 64 -ptx_opcode_initiation_int 1,2,2,1,8,4 # Opcode initiation intervals for integers <ADD,MAX,MUL,MAD,DIV,SHFL>Default 1,1,4,4,32,4 -ptx_opcode_initiation_fp 1,2,1,1,4 # Opcode initiation intervals for single precision floating points <ADD,MAX,MUL,MAD,DIV>Default 1,1,1,1,5 -ptx_opcode_initiation_dp 8,16,8,8,130 # Opcode initiation intervals for double precision floating points <ADD,MAX,MUL,MAD,DIV>Default 8,8,8,8,130 -ptx_opcode_initiation_sfu 8 # Opcode initiation intervals for sfu instructionsDefault 8 -ptx_opcode_initiation_tensor 64 # Opcode initiation intervals for tensor instructionsDefault 64 -cdp_latency 7200,8000,100,12000,1600 # CDP API latency <cudaStreamCreateWithFlags, cudaGetParameterBufferV2_init_perWarp, cudaGetParameterBufferV2_perKernel, cudaLaunchDeviceV2_init_perWarp, cudaLaunchDevicV2_perKernel>Default 7200,8000,100,12000,1600 -network_mode 1 # Interconnection network mode -inter_config_file config_fermi_islip.icnt # Interconnection network config file -inct_in_buffer_limit 64 # in_buffer_limit -inct_out_buffer_limit 64 # out_buffer_limit -inct_subnets 2 # subnets -gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries -gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable] -checkpoint_option 0 # checkpointing flag (0 = no checkpoint) -checkpoint_kernel 1 # checkpointing during execution of which kernel (1- 1st kernel) -checkpoint_CTA 0 # checkpointing after # of CTA (< less than total CTA) -resume_option 0 # resume flag (0 = no resume) -resume_kernel 0 # Resume from which kernel (1= 1st kernel) -resume_CTA 0 # resume from which CTA -checkpoint_CTA_t 0 # resume from which CTA -checkpoint_insn_Y 0 # resume from which CTA -gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus -gpgpu_ptx_force_max_capability 20 # Force maximum compute capability -gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file -gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file -gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output -gpgpu_simd_model 1 # 1 = post-dominator ... ` Sometimes I want to focus on application debuging. And I have log file to trace hardware data, these ouput is not necessary. Can I turn off it if it is not needed?

mattsinc commented 4 years ago

Those specific prints only happen once at the beginning of your run. But, if you want to turn them off while leaving the prints in the code, you could use the g_debug_execution flag (which is set based on the PTX_SIM_DEBUG environment variable). You can look around in the simulator and see other instances of this -- basically, the higher you set the debug level, the more prints you'll see. For example, you could make the prints you want to remove be at debug level 1, and then set PTX_SIM_DEBUG to 0 and they wouldn't print.

Matt

brad-mengchi commented 4 years ago

The output you showed here is GPGPU-Sim configuration. You can "export PTX_SIM_DEBUG=0" to avoid much info prints inside GPGPU-Sim, but I am not sure whether you can avoid the configuration prints with this env variable.

If it is not working and you really want to avoid those prints as much as possible, an ugly fix could be:

  1. comment out this line(https://github.com/gpgpu-sim/gpgpu-sim_distribution/blob/master/src/option_parser.cc#L417) for options inside GPGPU-Sim.

  2. Fix fout to be stderr(https://github.com/gpgpu-sim/gpgpu-sim_distribution/blob/master/src/option_parser.cc#L417) for options and redirect stderr stream into another file.

KMFtcy commented 4 years ago

Those specific prints only happen once at the beginning of your run. But, if you want to turn them off while leaving the prints in the code, you could use the g_debug_execution flag (which is set based on the PTX_SIM_DEBUG environment variable). You can look around in the simulator and see other instances of this -- basically, the higher you set the debug level, the more prints you'll see. For example, you could make the prints you want to remove be at debug level 1, and then set PTX_SIM_DEBUG to 0 and they wouldn't print.

Matt @mattsinc Hi Matt! Sorry for my late reply. And many thanks for your help! I wonder when should I use the g_debug_execution flag? I've set PTX_SIM_DEBUG to 0 with "export PTX_SIM_DEBUG=0" command but nothing changed. I change gpgpu_ptx_sim_mode varrible in gpgpusim.config to 1 and less ouput show up, which kind of solve my problem. But I also lost all message in log file......

KMFtcy commented 4 years ago

The output you showed here is GPGPU-Sim configuration. You can "export PTX_SIM_DEBUG=0" to avoid much info prints inside GPGPU-Sim, but I am not sure whether you can avoid the configuration prints with this env variable.

If it is not working and you really want to avoid those prints as much as possible, an ugly fix could be:

  1. comment out this line(https://github.com/gpgpu-sim/gpgpu-sim_distribution/blob/master/src/option_parser.cc#L417) for options inside GPGPU-Sim.
  2. Fix fout to be stderr(https://github.com/gpgpu-sim/gpgpu-sim_distribution/blob/master/src/option_parser.cc#L417) for options and redirect stderr stream into another file.

@echoedit Hi echoedit! Sorry for replying late and many thanks for your advice! I've tried what you suggest but nothing change. There are still lots of PTX messages pump out, I show them below : ...... GPGPU-Sim: synchronize waiting for inactive GPU simulation GPGPU-Sim API: Stream Manager State GPGPU-Sim: detected inactive GPU simulation thread

of blocks = 10000, # of threads/block = 256 (ensure that device can handle)

GPGPU-Sim PTX: Setting up arguments for 8 bytes starting at 0x7ffc96b9d1c8.. GPGPU-Sim PTX: Setting up arguments for 8 bytes starting at 0x7ffc96b9d1c0.. GPGPU-Sim PTX: Setting up arguments for 8 bytes starting at 0x7ffc96b9d1b8.. GPGPU-Sim PTX: Setting up arguments for 8 bytes starting at 0x7ffc96b9d1b0.. GPGPU-Sim PTX: Setting up arguments for 8 bytes starting at 0x7ffc96b9d1a8.. GPGPU-Sim PTX: Setting up arguments for 8 bytes starting at 0x7ffc96b9d1a0.. GPGPU-Sim PTX: Setting up arguments for 8 bytes starting at 0x7ffc96b9d1e0.. GPGPU-Sim PTX: Setting up arguments for 8 bytes starting at 0x7ffc96b9d1e8..

GPGPU-Sim PTX: cudaLaunch for 0x0x55fd457fb170 (mode=functional simulation) on stream 0 GPGPU-Sim PTX: finding reconvergence points for 'findK'... GPGPU-Sim PTX: Finding dominators for 'findK'... GPGPU-Sim PTX: Finding immediate dominators for 'findK'... GPGPU-Sim PTX: Finding postdominators for 'findK'... GPGPU-Sim PTX: Finding immediate postdominators for 'findK'... GPGPU-Sim PTX: pre-decoding instructions for 'findK'... GPGPU-Sim PTX: reconvergence points for findK... GPGPU-Sim PTX: 1 (potential) branch divergence @ PC=0x0d0 (b+tree.1.sm_60.ptx:57) @%p8 bra BB0_54; GPGPU-Sim PTX: immediate post dominator @ PC=0x808 (b+tree.1.sm_60.ptx:372) setp.ne.s32%p35, %r94, %r93; GPGPU-Sim PTX: 2 (potential) branch divergence @ PC=0x108 (b+tree.1.sm_60.ptx:65) @%p9 bra BB0_2; GPGPU-Sim PTX: immediate post dominator @ PC=0x440 (b+tree.1.sm_60.ptx:209) cvt.s64.s32%rd15, %r34; GPGPU-Sim PTX: 3 (potential) branch divergence @ PC=0x118 (b+tree.1.sm_60.ptx:68) @%p10 bra BB0_4; GPGPU-Sim PTX: immediate post dominator @ PC=0x330 (b+tree.1.sm_60.ptx:164) setp.gt.s32%p18, %r94, %r93; GPGPU-Sim PTX: 4 (potential) branch divergence @ PC=0x120 (b+tree.1.sm_60.ptx:69) bra.uni BB0_5; GPGPU-Sim PTX: immediate post dominator @ PC=0x150 (b+tree.1.sm_60.ptx:81) setp.eq.s64%p11, %rd45, 2; GPGPU-Sim PTX: 5 (potential) branch divergence @ PC=0x130 (b+tree.1.sm_60.ptx:73) bra.uni BB0_20; GPGPU-Sim PTX: immediate post dominator @ PC=0x330 (b+tree.1.sm_60.ptx:164) setp.gt.s32%p18, %r94, %r93; GPGPU-Sim PTX: 6 (potential) branch divergence @ PC=0x148 (b+tree.1.sm_60.ptx:78) bra.uni BB0_27; GPGPU-Sim PTX: immediate post dominator @ PC=0x440 (b+tree.1.sm_60.ptx:209) cvt.s64.s32%rd15, %r34; GPGPU-Sim PTX: 7 (potential) branch divergence @ PC=0x158 (b+tree.1.sm_60.ptx:82) @%p11 bra BB0_13; GPGPU-Sim PTX: immediate post dominator @ PC=0x238 (b+tree.1.sm_60.ptx:122) setp.gt.s32%p15, %r94, %r93; GPGPU-Sim PTX: 8 (potential) branch divergence @ PC=0x168 (b+tree.1.sm_60.ptx:85) @%p12 bra BB0_10; GPGPU-Sim PTX: immediate post dominator @ PC=0x1c8 (b+tree.1.sm_60.ptx:102) setp.eq.s32%p1, %r34, 0; GPGPU-Sim PTX: 9 (potential) branch divergence @ PC=0x180 (b+tree.1.sm_60.ptx:89) @%p13 bra BB0_10; GPGPU-Sim PTX: immediate post dominator @ PC=0x1c8 (b+tree.1.sm_60.ptx:102) setp.eq.s32%p1, %r34, 0; GPGPU-Sim PTX: 10 (potential) branch divergence @ PC=0x1b8 (b+tree.1.sm_60.ptx:97) @%p14 bra BB0_10; GPGPU-Sim PTX: immediate post dominator @ PC=0x1c8 (b+tree.1.sm_60.ptx:102) setp.eq.s32%p1, %r34, 0; GPGPU-Sim PTX: 11 (potential) branch divergence @ PC=0x1d8 (b+tree.1.sm_60.ptx:104) @!%p1 bra BB0_12; GPGPU-Sim PTX: immediate post dominator @ PC=0x1f8 (b+tree.1.sm_60.ptx:112) bar.sync 0; GPGPU-Sim PTX: 12 (potential) branch divergence @ PC=0x1e0 (b+tree.1.sm_60.ptx:105) bra.uni BB0_11; GPGPU-Sim PTX: immediate post dominator @ PC=0x1e8 (b+tree.1.sm_60.ptx:108) ld.global.u64 %rd54, [%rd4]; GPGPU-Sim PTX: 13 (potential) branch divergence @ PC=0x240 (b+tree.1.sm_60.ptx:123) @%p15 bra BB0_17; GPGPU-Sim PTX: immediate post dominator @ PC=0x2c8 (b+tree.1.sm_60.ptx:145) setp.eq.s32%p2, %r34, 0; GPGPU-Sim PTX: 14 (potential) branch divergence @ PC=0x280 (b+tree.1.sm_60.ptx:132) @%p16 bra BB0_17; GPGPU-Sim PTX: immediate post dominator @ PC=0x2c8 (b+tree.1.sm_60.ptx:145) setp.eq.s32%p2, %r34, 0; GPGPU-Sim PTX: 15 (potential) branch divergence @ PC=0x2b8 (b+tree.1.sm_60.ptx:140) @%p17 bra BB0_17; GPGPU-Sim PTX: immediate post dominator @ PC=0x2c8 (b+tree.1.sm_60.ptx:145) setp.eq.s32%p2, %r34, 0; GPGPU-Sim PTX: 16 (potential) branch divergence @ PC=0x2d8 (b+tree.1.sm_60.ptx:147) @!%p2 bra BB0_19; GPGPU-Sim PTX: immediate post dominator @ PC=0x2f8 (b+tree.1.sm_60.ptx:155) bar.sync 0; GPGPU-Sim PTX: 17 (potential) branch divergence @ PC=0x2e0 (b+tree.1.sm_60.ptx:148) bra.uni BB0_18; GPGPU-Sim PTX: immediate post dominator @ PC=0x2e8 (b+tree.1.sm_60.ptx:151) ld.global.u64 %rd74, [%rd4]; GPGPU-Sim PTX: 18 (potential) branch divergence @ PC=0x338 (b+tree.1.sm_60.ptx:165) @%p18 bra BB0_24; GPGPU-Sim PTX: immediate post dominator @ PC=0x3c0 (b+tree.1.sm_60.ptx:187) setp.eq.s32%p3, %r34, 0; GPGPU-Sim PTX: 19 (potential) branch divergence @ PC=0x378 (b+tree.1.sm_60.ptx:174) @%p19 bra BB0_24; GPGPU-Sim PTX: immediate post dominator @ PC=0x3c0 (b+tree.1.sm_60.ptx:187) setp.eq.s32%p3, %r34, 0; GPGPU-Sim PTX: 20 (potential) branch divergence @ PC=0x3b0 (b+tree.1.sm_60.ptx:182) @%p20 bra BB0_24; GPGPU-Sim PTX: immediate post dominator @ PC=0x3c0 (b+tree.1.sm_60.ptx:187) setp.eq.s32%p3, %r34, 0; GPGPU-Sim PTX: 21 (potential) branch divergence @ PC=0x3d0 (b+tree.1.sm_60.ptx:189) @!%p3 bra BB0_26; GPGPU-Sim PTX: immediate post dominator @ PC=0x3f0 (b+tree.1.sm_60.ptx:197) bar.sync 0; GPGPU-Sim PTX: 22 (potential) branch divergence @ PC=0x3d8 (b+tree.1.sm_60.ptx:190) bra.uni BB0_25; GPGPU-Sim PTX: immediate post dominator @ PC=0x3e0 (b+tree.1.sm_60.ptx:193) ld.global.u64 %rd94, [%rd4]; GPGPU-Sim PTX: 23 (potential) branch divergence @ PC=0x450 (b+tree.1.sm_60.ptx:211) @%p21 bra BB0_28; GPGPU-Sim PTX: immediate post dominator @ PC=0x808 (b+tree.1.sm_60.ptx:372) setp.ne.s32%p35, %r94, %r93; GPGPU-Sim PTX: 24 (potential) branch divergence @ PC=0x458 (b+tree.1.sm_60.ptx:212) bra.uni BB0_29; GPGPU-Sim PTX: immediate post dominator @ PC=0x478 (b+tree.1.sm_60.ptx:220) setp.gt.s32%p22, %r94, %r93; GPGPU-Sim PTX: 25 (potential) branch divergence @ PC=0x470 (b+tree.1.sm_60.ptx:217) bra.uni BB0_54; GPGPU-Sim PTX: immediate post dominator @ PC=0x808 (b+tree.1.sm_60.ptx:372) setp.ne.s32%p35, %r94, %r93; GPGPU-Sim PTX: 26 (potential) branch divergence @ PC=0x480 (b+tree.1.sm_60.ptx:221) @%p22 bra BB0_33; GPGPU-Sim PTX: immediate post dominator @ PC=0x508 (b+tree.1.sm_60.ptx:243) setp.eq.s32%p4, %r34, 0; GPGPU-Sim PTX: 27 (potential) branch divergence @ PC=0x4c0 (b+tree.1.sm_60.ptx:230) @%p23 bra BB0_33; GPGPU-Sim PTX: immediate post dominator @ PC=0x508 (b+tree.1.sm_60.ptx:243) setp.eq.s32%p4, %r34, 0; GPGPU-Sim PTX: 28 (potential) branch divergence @ PC=0x4f8 (b+tree.1.sm_60.ptx:238) @%p24 bra BB0_33; GPGPU-Sim PTX: immediate post dominator @ PC=0x508 (b+tree.1.sm_60.ptx:243) setp.eq.s32%p4, %r34, 0; GPGPU-Sim PTX: 29 (potential) branch divergence @ PC=0x518 (b+tree.1.sm_60.ptx:245) @!%p4 bra BB0_35; GPGPU-Sim PTX: immediate post dominator @ PC=0x538 (b+tree.1.sm_60.ptx:253) bar.sync 0; GPGPU-Sim PTX: 30 (potential) branch divergence @ PC=0x520 (b+tree.1.sm_60.ptx:246) bra.uni BB0_34; GPGPU-Sim PTX: immediate post dominator @ PC=0x528 (b+tree.1.sm_60.ptx:249) ld.global.u64 %rd116, [%rd4]; GPGPU-Sim PTX: 31 (potential) branch divergence @ PC=0x588 (b+tree.1.sm_60.ptx:263) @%p25 bra BB0_39; GPGPU-Sim PTX: immediate post dominator @ PC=0x5e8 (b+tree.1.sm_60.ptx:280) bar.sync 0; GPGPU-Sim PTX: 32 (potential) branch divergence @ PC=0x5a0 (b+tree.1.sm_60.ptx:267) @%p26 bra BB0_39; GPGPU-Sim PTX: immediate post dominator @ PC=0x5e8 (b+tree.1.sm_60.ptx:280) bar.sync 0; GPGPU-Sim PTX: 33 (potential) branch divergence @ PC=0x5d8 (b+tree.1.sm_60.ptx:275) @%p27 bra BB0_39; GPGPU-Sim PTX: immediate post dominator @ PC=0x5e8 (b+tree.1.sm_60.ptx:280) bar.sync 0; GPGPU-Sim PTX: 34 (potential) branch divergence @ PC=0x5f0 (b+tree.1.sm_60.ptx:281) @!%p4 bra BB0_41; GPGPU-Sim PTX: immediate post dominator @ PC=0x610 (b+tree.1.sm_60.ptx:289) bar.sync 0; GPGPU-Sim PTX: 35 (potential) branch divergence @ PC=0x5f8 (b+tree.1.sm_60.ptx:282) bra.uni BB0_40; GPGPU-Sim PTX: immediate post dominator @ PC=0x600 (b+tree.1.sm_60.ptx:285) ld.global.u64 %rd128, [%rd4]; GPGPU-Sim PTX: 36 (potential) branch divergence @ PC=0x658 (b+tree.1.sm_60.ptx:298) @%p28 bra BB0_45; GPGPU-Sim PTX: immediate post dominator @ PC=0x6b8 (b+tree.1.sm_60.ptx:315) bar.sync 0; GPGPU-Sim PTX: 37 (potential) branch divergence @ PC=0x670 (b+tree.1.sm_60.ptx:302) @%p29 bra BB0_45; GPGPU-Sim PTX: immediate post dominator @ PC=0x6b8 (b+tree.1.sm_60.ptx:315) bar.sync 0; GPGPU-Sim PTX: 38 (potential) branch divergence @ PC=0x6a8 (b+tree.1.sm_60.ptx:310) @%p30 bra BB0_45; GPGPU-Sim PTX: immediate post dominator @ PC=0x6b8 (b+tree.1.sm_60.ptx:315) bar.sync 0; GPGPU-Sim PTX: 39 (potential) branch divergence @ PC=0x6c0 (b+tree.1.sm_60.ptx:316) @!%p4 bra BB0_47; GPGPU-Sim PTX: immediate post dominator @ PC=0x6e0 (b+tree.1.sm_60.ptx:324) bar.sync 0; GPGPU-Sim PTX: 40 (potential) branch divergence @ PC=0x6c8 (b+tree.1.sm_60.ptx:317) bra.uni BB0_46; GPGPU-Sim PTX: immediate post dominator @ PC=0x6d0 (b+tree.1.sm_60.ptx:320) ld.global.u64 %rd140, [%rd4]; GPGPU-Sim PTX: 41 (potential) branch divergence @ PC=0x728 (b+tree.1.sm_60.ptx:333) @%p31 bra BB0_51; GPGPU-Sim PTX: immediate post dominator @ PC=0x788 (b+tree.1.sm_60.ptx:350) bar.sync 0; GPGPU-Sim PTX: 42 (potential) branch divergence @ PC=0x740 (b+tree.1.sm_60.ptx:337) @%p32 bra BB0_51; GPGPU-Sim PTX: immediate post dominator @ PC=0x788 (b+tree.1.sm_60.ptx:350) bar.sync 0; GPGPU-Sim PTX: 43 (potential) branch divergence @ PC=0x778 (b+tree.1.sm_60.ptx:345) @%p33 bra BB0_51; GPGPU-Sim PTX: immediate post dominator @ PC=0x788 (b+tree.1.sm_60.ptx:350) bar.sync 0; GPGPU-Sim PTX: 44 (potential) branch divergence @ PC=0x790 (b+tree.1.sm_60.ptx:351) @!%p4 bra BB0_53; GPGPU-Sim PTX: immediate post dominator @ PC=0x7b0 (b+tree.1.sm_60.ptx:359) bar.sync 0; GPGPU-Sim PTX: 45 (potential) branch divergence @ PC=0x798 (b+tree.1.sm_60.ptx:352) bra.uni BB0_52; GPGPU-Sim PTX: immediate post dominator @ PC=0x7a0 (b+tree.1.sm_60.ptx:355) ld.global.u64 %rd152, [%rd4]; GPGPU-Sim PTX: 46 (potential) branch divergence @ PC=0x800 (b+tree.1.sm_60.ptx:369) @%p34 bra BB0_29; GPGPU-Sim PTX: immediate post dominator @ PC=0x808 (b+tree.1.sm_60.ptx:372) setp.ne.s32%p35, %r94, %r93; GPGPU-Sim PTX: 47 (potential) branch divergence @ PC=0x810 (b+tree.1.sm_60.ptx:373) @%p35 bra BB0_56; GPGPU-Sim PTX: immediate post dominator @ PC=0x870 (b+tree.1.sm_60.ptx:388) ret; GPGPU-Sim PTX: ... end of reconvergence points for findK GPGPU-Sim PTX: ... done pre-decoding instructions for 'findK'. GPGPU-Sim PTX: pushing kernel 'findK' to stream 0, gridDim= (10000,1,1) blockDim = (256,1,1) GPGPU-Sim: Performing Functional Simulation, executing kernel findK... GPGPU-Sim PTX: PDOM analysis already done for findK ......

These are only part of the redundant ouput. Further more,I change gpgpu_ptx_sim_mode varrible in gpgpusim.config to 1 and less ouput show up, which kind of solve my problem. But I also lost all message in log file, that I'm not willing to see.