Open jennalwise opened 1 year ago
Along a similar vain, if you have your specs split across two clauses, like two ensures clauses, conditionals still take precedence. For example, I expected
//@ ensures ? && acc(*rest) && acc(\result->name) && (\result->name == NULL ? true : *rest != gv_tok);
//@ ensures tokenListSeg(gv_tok, *rest) && tokenListSeg(*rest, NULL);
to join into:
//@ ensures ? && acc(*rest) && acc(\result->name) && (\result->name == NULL ? true : *rest != gv_tok) && tokenListSeg(gv_tok, *rest) && tokenListSeg(*rest, NULL);
But, in reality the frontend turned it into:
//@ ensures ? && acc(*rest) && acc(\result->name) && (\result->name == NULL ? true : *rest != gv_tok && tokenListSeg(gv_tok, *rest) && tokenListSeg(*rest, NULL));
for the backend.
If what Gradual C0 is doing here is the right thing, then we need to probably warn or make it clear to the user that this isn't the intention. Otherwise, we should probably fix the behavior here to match my expected version (especially since I include parentheses around the conditional).
In my case study, I wrote a loop invariant:
tokenListSeg(gv_tok, tok) && gv_beforeloop == true ? true : gv_tok != tok
which is ambiguous and with conditional priority makes sense to translate into:
(tokenListSeg(gv_tok,tok) && gv_beforeloop == true ? true : gv_tok != tok)
which interpretstokenListSeg(gv_tok,tok)
as being in the condition of the logical conditional. This is not my intention, and I'm okay with having to adjust my specification. However, the error I got due to the 'bad' spec was a Scala Match error from the silicon backend:At the very least this should not happen, because the only way I was able to figure out that my specification was bad was from putting the .vpr file in silicon-gv directly which utilizes the silver-gv parser and catches my bad spec as a consistency error:
At minimum, Gradual C0 should produce the same error. But, maybe we could do better in some way?