upduino: fails timing

[osresearch]

Checked out 47046ca38ded889108630c7ee964093b827691b5 and ran make BOARD=upduino:

nextpnr-ice40 -q --up5k --package sg48 --json top.json --pcf boards/upduino.pcf --freq 24 --asc top_syn.asc
ERROR: Max frequency for clock 'flash_clk_$glb_clk': 13.56 MHz (FAIL at 24.00 MHz)
0 warnings, 1 error
arch/ice40.mk:16: recipe for target 'top_syn.asc' failed

This is with:

nextpnr-ice40 -- Next Generation Place and Route (git sha1 eb456ef)
arachne-pnr 0.1+310+0 (git sha1 5d830dd, g++ 5.4.0-6ubuntu1~16.04.9 -O2)
riscv64-unknown-elf-gcc (GCC) 8.2.0

[osresearch]

At 24 MHz the hello world resets frequently. At 16 MHz more complex programs work, but it still resets if some instructions are used (like division?)

[tomtor]

@osresearch I am waiting for the mail to deliver my upduino, but I created a patch to use the 12 Mhz oscillator:

EDIT: https://github.com/tomtor/icicle/tree/upduino_osc

Can you test it? I will test it myself as soon as I have the hardware. If it works I'll create a PR.

[grahamedgecombe]

I don't have any UltraPlus devices (...yet, eagerly awaiting iCEBreaker+Fomu!) so the support isn't particularly well-tested.

I've made the bypassing + branch prediction optional (and disabled by default). This increases the maximum clock frequency on UP5K devices to ~20 MHz, which is now above 16 MHz (the lowest clock speed support by the PLL). I've dropped FREQ_PLL to 16 for UP5K devices, so it should work out the box now.