latticesakita commented 6 years ago

Hi, opcode is 7bits width but it is declared as 8bits in rv32_fetch.sv. it should be below.

logic [6:0] opcode; assign opcode = instr_read_value_in[6:0];

Hope you will update, Regards, Sakita

grahamedgecombe commented 6 years ago

Thanks, this has actually unearthed another issue - the branch prediction doesn't work properly! I'm looking at that at the moment...

grahamedgecombe commented 6 years ago

Finally (!) fixed in the following series of commits:

afbd4ff0e223865c6198c2dbcb4e9fedd1191d9f - fixes opcode width
5b2e7be813de6a182d12d9273909f87f496dfd7c - fixes branch PC for mispredicted as taken branches
567ead196f303bff92b244db5e33cc814fba994e - fixes branch prediction case statement (which hid the original opcode bug)
769db55c10cfbada0b909351a22f278b41fa2abc - updates PC if a branch is mispredicted during a fetch stall (I don't think this case can happen yet as a fetch stall can only happen during a memory access instruction atm, but branch mispredictions are also resolved during the memory access stage. But it'll be needed if/when memory-mapped SPI flash is added.)
21f50e5ef39cb6da41d643deb839e82349f7f048 - set branch_predicted_taken to 0 if decode/execute are flushed (took me ages to find this! If decode/execute is flushed then branch_op is always set to NEVER, but if branch_predicted_taken happens to be 1 then the pipeline bubble isn't actually a no-op like it's supposed to be.)