iverilog?

[tomverbeure]

I'm intrigued by this: https://github.com/grahamedgecombe/icicle/blob/e87ce65ff879b8eb59210f897d4e46ec08f94a0c/Makefile#L52

When I run 'make syntax', I get tons of syntax errors, which makes me believe that iverilog still doesn't support the most basic SystemVerilog constructs.

But did you get any benefit from putting it in the Makefile?

Did you simulate your design in some other way?

Tom

[tomverbeure]

My current assumption is that iverilog doesn't work with icicle.

So I went ahead and did the following:

• replace all 'logic' by 'reg'
• replace all 'always_comb' by 'always @*'
• replace all 'always_ff' by 'always @(posedge clk)

See this commit: https://github.com/tomverbeure/icicle/commit/f3ed30394b05819622cd99cad082711712b6cc29

After that, iverilog successfully compiles the code.

Since the code doesn't use any other SystemVerilog specific constructs (as far as I can see), it may be better for compatibility reasons to move over the code to that.

Tom

[grahamedgecombe]

You need the master branch of iverilog (as per the README), the always_comb/ff support hasn't been included in a stable release yet.

[tomverbeure]

Ok. I have the latest master on my main development machine, but the master branch on my laptop was a bit older.

Closing.