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grahamedgecombe / icicle

32-bit RISC-V system on chip for iCE40 FPGAs
ISC License
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CPU doesn't have any reset. #8

Closed tomverbeure closed 6 years ago

tomverbeure commented 6 years ago

When trying to simulate the CPU (after my SV to Verilog conversion of issue #7), I ran into the problem that none of the FFs of the CPU are reseted.

While it's correct to assume that all FFs in an FPGA will power up with a value of 0, this still makes it impossible to simulate the design on anything other than a simulator that only supports the 0 and 1 state (such as Verilator.)

I have a commit that resets all FFs to 0: https://github.com/tomverbeure/icicle/commit/e1ae96391aa9b556abcffb608f45842b7a4858f5

After this fix, the CPU comes alive after releasing the reset_.

This fix is really essential to make the code generally usable.

Tom

grahamedgecombe commented 6 years ago

thanks, merged :smiley: