grandideastudio / jtagulator

JTAGulator: Assisted discovery of on-chip debug interfaces
https://grandideastudio.com/portfolio/security/jtagulator/
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jtagulator pin identification problem #44

Closed yum7777 closed 3 years ago

yum7777 commented 3 years ago

Hello,

I used the jtagulator tool on my test board.

However, the jtagulator tool was unable to identify the pin.

Did I use it wrong?

Or is there another problem?

The pin order has already been identified.

Connection was successful through jtag emulator.

                                    UU  LLL
 JJJ  TTTTTTT AAAAA  GGGGGGGGGGG   UUUU LLL   AAAAA TTTTTTTT OOOOOOO  RRRRRRRRR
 JJJJ TTTTTTT AAAAAA GGGGGGG       UUUU LLL  AAAAAA TTTTTTTT OOOOOOO  RRRRRRRR
 JJJJ  TTTT  AAAAAAA GGG      UUU  UUUU LLL  AAA AAA   TTT  OOOO OOO  RRR RRR
 JJJJ  TTTT  AAA AAA GGG  GGG UUUU UUUU LLL AAA  AAA   TTT  OOO  OOO  RRRRRRR
 JJJJ  TTTT  AAA  AA GGGGGGGGG UUUUUUUU LLLLLLLL AAAA  TTT OOOOOOOOO  RRR RRR
  JJJ  TTTT AAA   AA GGGGGGGGG UUUUUUUU LLLLLLLLL AAA  TTT OOOOOOOOO  RRR RRR
  JJJ  TT                  GGG             AAA                         RR RRR
 JJJ                        GG             AA                              RRR
JJJ                          G             A                                 RR

           Welcome to JTAGulator. Press 'H' for available commands.
         Warning: Use of this tool may affect target system behavior!

> v
Current target I/O voltage: Undefined
Enter new target I/O voltage (1.4 - 3.3, 0 for off): 3.3
New target I/O voltage set: 3.3
Warning: Ensure VADJ is NOT connected to target!

> j

JTAG> j
Enter starting channel [0]: 0
Enter ending channel [0]: 8
Possible permutations: 3024

Bring channels LOW before each permutation? [y/N]: n
Press spacebar to begin (any other key to abort)...
JTAGulating! Press any key to abort...
-----
No target device(s) found!
JTAG scan complete.

0: TRST 1: TMS 2: TDI 3: TDO 4: TCK

image

Logic analysis results : 16 MHz, 160 M Samples [12].zip

joegrand commented 3 years ago

There are many reasons the JTAGulator might not detect the interface. Please see item 2 from the FAQ.

It appears that TRST is still being held low during your logic analyzer capture. If that remains LOW, as already mentioned in #43, the JTAG TAP will not be enabled properly. It's possible that your JTAG hardware (which you're calling "emulator") is properly pulling the TRST pin high or doing something with additional pins that are required in order for JTAG to become active.

It's also possible that there's an issue between the target and JTAGulator's front end. The relevant discussion is at #3 and may require modifying the JTAGulator's front end. I wouldn't jump to that conclusion right away, though.

Also, as mentioned in the FAQ, the more information you provide, the easier it will be to help debug your issues in the future. Please provide as much information as possible about your environment, including a description of your target hardware, high-resolution photos showing connections/wiring, and screenshots or log files showing JTAGulator output. I'd also suggest checking out the JTAGulator slides and videos linked at item 1 in the FAQ.