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grantslape
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CS3339-MIPS32
5 stage, pipelined MIPS32 processor in myHDL and Verilog
GNU General Public License v3.0
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Project structure and Initial tests
#2
Closed
grantslape
closed
6 years ago
grantslape
commented
6 years ago
Basic Project structure
src
,
test
,
docs
.
Pip requirements
Beginnings of test framework
Note we still have some work to do, such as usable globals from
settings.py
, and
test_all_modules.py
src
,test
,docs
.settings.py
, andtest_all_modules.py