grantslape / CS3339-MIPS32

5 stage, pipelined MIPS32 processor in myHDL and Verilog
GNU General Public License v3.0
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Titans mm dev 1 #24

Closed TitansMM closed 6 years ago

TitansMM commented 6 years ago

I uploaded inst_mem.v, inst_mem_tb.v, inst_mem.py, and instructions.bin, in each src folder. Let me know what you think. I might need to add an argument to the verilog module to accept a size parameter, for the array.