Byte Addressing vs. Word Addressing

[grantslape]

Typically in the MIPS architecture instruction memory and data memory come from the same general main memory. For the purposes of this pipeline however, the instruction memory and data memory buffers are separate.

This creates an issue with how we access instructions. We increment the PC by 4 each cycle in the pc_adder, but the next sequential instruction differs in address by 1.

I believe the fix here will be to take actual_index = incoming_instruction_address % 4 inside the instruction memory itself, since that module is what differs from the typical architecture.

This will involve updates to the following:

• inst_mem.py
• inst_mem.v
• inst_mem_tb.v
• test_inst_mem.py

[TitansMM]

I made some changes to all four files that I think resolved the problem.

[grantslape]

I agree, Isaac and I solved this problem in #43

[grantslape]

Realized we had another issue that is resolved by #47