grantslape / CS3339-MIPS32

5 stage, pipelined MIPS32 processor in myHDL and Verilog
GNU General Public License v3.0
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Support for Arbitrarily Long Simulations #49

Closed grantslape closed 6 years ago

grantslape commented 6 years ago

Issue

Currently our processor is limited to 1M (2 ^ 20) instructions via a static array size. Our project requirements need us to support an arbitrarily long simulation, with numbers in the several million being thrown around.

Given these parameters, eventually we are going to reach the last instruction in our array, and we need to ensure that we do not step out of bounds and cause the simulation to fail.

Implementation

We can get around this by always generating an unconditional jump to the beginning as the last instruction. in assembly this instruction would be j 0x0

This will work as follows: