This can result in Apollo claiming the CONTROL port on Cynthion instead of handing it off to the FPGA shortly after start-up.
Due to a quirk of Apollo's behavior, some gateware that starts requesting the CONTROL port early at start-up can gain control of the port, but this is unreliable due to unpredictable timing (presumably FPGA PLL start-up).
This can result in Apollo claiming the CONTROL port on Cynthion instead of handing it off to the FPGA shortly after start-up.
Due to a quirk of Apollo's behavior, some gateware that starts requesting the CONTROL port early at start-up can gain control of the port, but this is unreliable due to unpredictable timing (presumably FPGA PLL start-up).