Closed rlewkowicz closed 1 month ago
mossmann
commented
1 month ago FPGA pin numbers such as F2 in the hardware design and in the LUNA/Cynthion platform files correspond to the CABGA256 column in the ECP5 pinout spreadsheet you linked. We use the CABGA256 package.
When you say you'd like to create another RAM resource, what do you mean exactly? Are you modifying the hardware design? Are you wanting to connect an add-on board via the mezzanine or Pmod connectors?
rlewkowicz
commented
1 month ago I think technically I'm building my own Dual Clock FIFO (FIFO_DC) (maybe even tri clock, but the way I write it, it might not matter): https://www.latticesemi.com/view_document?document_id=50466
I still dont fully get the clocks. I know the buses have to be synced. But can each do their own and I use this double fifo for handoff?
I think your fifo implementation is close. Really all I have to add is AlmostEmpty flags I think. That might not be as easy as I think. Although none of this has been easy lol.
Ultimately, it seems that target phy is one object. Both A and C. I want to make a queue for Aux and Target. at 4096 I can make 3 queues (edit: oof or not, these are not 1024, I'll deal with it later. 2 queues for now). I need to replace upto 4 bytes in "real time". So the goal is, through vendor requests populate a 4 byte replacement buffer. As the buffers come in, scan for my target byte steam of 4b20 (idk what logic I can do yet) and if my replacement buffer is populated switch out bytes in real time from the replacement buffer x bytes later. You platform "ram" cannot be shared. I wonder if the depth could be an offset and it all uses one ram implementation. I don't know enough yet. For me it's easier to create new buffers if the pins are available than rewrite the hyper ram. It's all amaranth, idk if I can even get at that offset.
I'm still figuring out passive control etc. One queue should pump the other.
These are my musings. I'm sure there's a lot of off thoughts and misunderstanding. https://github.com/rlewkowicz/cynthion/blob/61b95d063812bb1113bc8ea45d96d13fe1658319/cynthion/python/src/gateware/dumbproxy/top.py#L130
Finally, I still have to wire it up, but I asked how to debug this. I think it's just UART is the answer. https://github.com/rlewkowicz/cynthion/blob/61b95d063812bb1113bc8ea45d96d13fe1658319/cynthion/python/src/gateware/dumbproxy/top.py#L74
The goal right now though is just 2 queues with one pumping the other in/out. Verify that works, then try for a third
rlewkowicz
commented
1 month ago While I got ya, I'm going to steal one more hardware related question, Does this pass power to aux? https://github.com/rlewkowicz/cynthion/blob/61b95d063812bb1113bc8ea45d96d13fe1658319/cynthion/python/src/gateware/dumbproxy/top.py#L144 If not what are the flags needed to pass to aux, not target A?
rlewkowicz
commented
1 month ago The only unused pins are?:
| 7 | PL5A | 7 | - | True_OF_PL5B | TRUE | LDQ8 | C1 |
| 42 | PL20D | 7 | - | Comp_OF_PL20C | - | LDQ20| K3 |
| 48 | PL23D | 7 | PCLKC7_0| Comp_OF_PL23C | - | LDQ20| K2 |In the ram platform, G4 is "high speed" but "F3" is not. B2 and C1 are high speed. But if I want another ram interface those pins are gone. I don't know the ramifications of these choices.
Can I just consume anyones pins? Can I take from other functions?
Idk what dqs is, the pin selection feels random?
This is probably not the intended scope of this product cause now we're just fpga programming. But this is cool. I just need to know more. Some data sheets like, discuss the pins for some fpgas.
edit: https://www.latticesemi.com/view_document?document_id=50461
They do to. So is what I'm doing functionally possible? Is the theory correct? Or I misunderstand something and I only get one ram? Even if I have to learn way more than I should, can it be done? Cause I can do anything with enough time.
rlewkowicz
commented
1 month ago +--------+-----+ +-----+----------+---------------+------+---------+-----+ +-------------------+--------+-------+ +--------------------+--------+-----------------+
| P[L/R] | | | PAD | Pin/Ball | Differential | HS | DQS | 256 | | Pin Type | bank | cabga | | Resource | Subsig | Pins |
| [nā6] | | +-----+----------+---------------+------+---------+-----+ +-------------------+--------+-------+ +--------------------+--------+-----------------+
+--------+-----+ | 1 | PL2A | True_OF_PL2B | TRUE | LDQ8 | B1 | | Inputs/Outputs | Bank 0 | 24 | | pseudo_vccio | | E6 E7 D10 E10 |
| A | DQ | | 2 | PL2B | Comp_OF_PL2A | TRUE | LDQ8 | B2 | | | Bank 1 | 32 | | | | E11 F12 J12 K12 |
| B | DQ | | 4 | PL2C | True_OF_PL2D | - | LDQ8 | C3 | | | Bank 2 | 32 | | | | L12 N13 P13 M11 |
| C | DQ | | 6 | PL2D | Comp_OF_PL2C | - | LDQ8 | D3 | | | Bank 3 | 32 | | | | P11 P12 L4 M4 |
| D | DQ | | 7 | PL5A | True_OF_PL5B | TRUE | LDQ8 | C1 | | | Bank 4 | 0 | | | | R5 M5 N5 P4 M6 |
+--------+-----+ | 9 | PL5C | True_OF_PL5D | - | LDQ8 | E3 | | | Bank 6 | 32 | | | | F5 G5 H5 H4 J4 |
| P[L/R] | | | 10 | PL5B | Comp_OF_PL5A | TRUE | LDQ8 | C2 | | | Bank 7 | 32 | | | | J5 J3 J1 J2 R6 |
| [nā3] | | | 12 | PL5D | Comp_OF_PL5C | - | LDQ8 | F3 | | | Bank 8 | 13 | +--------------------+--------+-----------------+
+--------+-----+ | 13 | PL8A | True_OF_PL8B | TRUE | LDQS8 | D1 | +-------------------+--------+-------+ | pseudo_gnd | | E5 E8 E9 E12 |
| A | DQ | | 15 | PL8C | True_OF_PL8D | - | LDQ8 | F4 | | Total User I/O | 98 | 118 | | | | F13 M13 M12 N12 |
| B | DQ | | 16 | PL8B | Comp_OF_PL8A | TRUE | LDQSN8 | E2 | +-------------------+--------+-------+ | | | N11 L5 L3 M3 N6 |
| C | DQ | | 18 | PL8D | Comp_OF_PL8C | - | LDQ8 | F5 | | VCC | 8 | 13 | | | | P5 P6 F4 G2 G3 |
| D | DQ | | 19 | PL11A | True_OF_PL11B | TRUE | LDQ8 | G5 | +-------------------+--------+-------+ | | | H3 H2 |
+--------+-----+ | 21 | PL11C | True_OF_PL11D | - | LDQ8 | F2 | | VCCAUX(Core) | 4 | 3 | +--------------------+--------+-----------------+
| P[L/R] | | | 22 | PL11B | Comp_OF_PL11A | TRUE | LDQ8 | G4 | +-------------------+--------+-------+ | clk_60MHz | | A8 |
| [n] | | | 24 | PL11D | Comp_OF_PL11C | - | LDQ8 | E1 | | VCCIO | Bank 0 | 2 | +--------------------+--------+-----------------+
+--------+-----+ | 25 | PL14A | True_OF_PL14B | TRUE | LDQ20 | F1 | | | Bank 1 | 2 | | spi_flash | sdi | T8 |
| A | DQS | | 27 | PL14C | True_OF_PL14D | - | LDQ20 | G3 | | | Bank 2 | 2 | | | sdo | T7 |
| B | DQS | | 28 | PL14B | Comp_OF_PL14A | TRUE | LDQ20 | G2 | | | Bank 3 | 2 | | | cs | N8 (PinsN) |
| C | DQ | | 30 | PL14D | Comp_OF_PL14C | - | LDQ20 | H3 | | | Bank 4 | 0 | +--------------------+--------+-----------------+
| D | DQ | | 31 | PL17A | True_OF_PL17B | TRUE | LDQ20 | H5 | | | Bank 6 | 2 | | qspi_flash | dq | T8 T7 M7 N7 |
+--------+-----+ | 33 | PL17C | True_OF_PL17D | - | LDQ20 | J4 | | | Bank 7 | 2 | | | cs | N8 (PinsN) |
| P[L/R] | | | 34 | PL17B | Comp_OF_PL17A | TRUE | LDQ20 | H4 | | | Bank 8 | 1 | +--------------------+--------+-----------------+
| [n+3] | | | 36 | PL17D | Comp_OF_PL17C | - | LDQ20 | J5 | +-------------------+--------+-------+ | uart | rx | R14 |
+--------+-----+ | 37 | PL20A | True_OF_PL20B | TRUE | LDQS20 | G1 | | TAP | 4 | 4 | | | tx | T14 |
| A | DQ | | 39 | PL20C | True_OF_PL20D | - | LDQ20 | J3 | +-------------------+--------+-------+ +--------------------+--------+-----------------+
| B | DQ | | 40 | PL20B | Comp_OF_PL20A | TRUE | LDQSN20 | H2 | | Miscellaneous | | | | int | | T6 |
| C | DQ | | 42 | PL20D | Comp_OF_PL20C | - | LDQ20 | K3 | | Dedicated Pins | 7 | | +--------------------+--------+-----------------+
| D | DQ | | 43 | PL23A | True_OF_PL23B | TRUE | LDQ20 | J1 | | GND | 27 | | | button_user | | M14 (PinsN) |
+--------+-----+ | 45 | PL23C | True_OF_PL23D | - | LDQ20 | K1 | | NC | 0 | | +--------------------+--------+-----------------+
| 46 | PL23B | Comp_OF_PL23A | TRUE | LDQ20 | J2 | | Reserved | 0 | | | self_program | | T13 (PinsN) |
| 48 | PL23D | Comp_OF_PL23C | - | LDQ20 | K2 | +-------------------+--------+-------+ +--------------------+--------+-----------------+
| 49 | PL26A | True_OF_PL26B | TRUE | LDQ32 | L1 | | Total Balls | 144 | 285 | | LEDs | | E13 C13 B14 |
| 51 | PL26C | True_OF_PL26D | - | LDQ32 | M1 | +-------------------+--------+-------+ | | | A15 D12 C11 |
| 52 | PL26B | Comp_OF_PL26A | TRUE | LDQ32 | L2 | | HS Diff I/O | Bank 0 | 0 | +--------------------+--------+-----------------+
| 54 | PL26D | Comp_OF_PL26C | - | LDQ32 | M2 | | | Bank 1 | 0 | | control_phy | data | N16 N14 P16 P15 |
| 55 | PL29A | True_OF_PL29B | TRUE | LDQ32 | K4 | | | Bank 2 | 16/8 | | | | R16 R15 T15 P14 |
| 57 | PL29C | True_OF_PL29D | - | LDQ32 | L4 | | | Bank 3 | 16/8 | | | clk | L14 |
| 58 | PL29B | Comp_OF_PL29A | TRUE | LDQ32 | K5 | | | Bank 4 | 0 | | | dir | M16 |
| 60 | PL29D | Comp_OF_PL29C | - | LDQ32 | L5 | | | Bank 6 | 16/8 | | | nxt | M15 |
| 61 | PL32A | True_OF_PL32B | TRUE | LDQS32 | N1 | | | Bank 7 | 16/8 | | | stp | L15 |
| 63 | PL32C | True_OF_PL32D | - | LDQ32 | L3 | | | Bank 8 | 0 | | | rst | L16 |
| 64 | PL32B | Comp_OF_PL32A | TRUE | LDQSN32 | P2 | +-------------------+--------+-------+ +--------------------+--------+-----------------+
| 66 | PL32D | Comp_OF_PL32C | - | LDQ32 | M3 | | Total HS Diff I/O | 28/16 | 45/27 | | aux_phy | data | F16 G15 G16 H15 |
| 67 | PL35A | True_OF_PL35B | TRUE | LDQ32 | P1 | +-------------------+--------+-------+ | | | J15 J16 K15 K16 |
| 69 | PL35C | True_OF_PL35D | - | LDQ32 | M4 | | DQS Groups | Bank 0 | 0 | | | clk | D16 |
| 70 | PL35B | Comp_OF_PL35A | TRUE | LDQ32 | R1 | | | Bank 1 | 0 | | | dir | E16 |
| 72 | PL35D | Comp_OF_PL35C | - | LDQ32 | N3 | | | Bank 2 | 2 | | | nxt | F15 |
| 73 | PL38A | True_OF_PL38B | TRUE | LDQ44 | N4 | | | Bank 3 | 2 | | | stp | E15 |
| 75 | PL38C | True_OF_PL38D | - | LDQ44 | R2 | | | Bank 4 | 0 | | | rst | J13 |
| 76 | PL38B | Comp_OF_PL38A | TRUE | LDQ44 | P3 | | | Bank 6 | 2 | +--------------------+--------+-----------------+
| 78 | PL38D | Comp_OF_PL38C | - | LDQ44 | T2 | | | Bank 7 | 2 | | target_phy | data | R2 R1 P2 P1 |
| 79 | PL41A | True_OF_PL41B | TRUE | LDQ44 | P4 | | | Bank 8 | 0 | | | | N3 N1 M2 M1 |
| 81 | PL41C | True_OF_PL41D | - | LDQ44 | R4 | +-------------------+--------+-------+ | | clk | T4 |
| 82 | PL41B | Comp_OF_PL41A | TRUE | LDQ44 | R3 | | Total DQS Groups | 8 | 6 | | | dir | R3 |
| 84 | PL41D | Comp_OF_PL41C | - | LDQ44 | T3 | +-------------------+--------+-------+ | | nxt | T2 |
| 85 | PL44A | True_OF_PL44B | TRUE | LDQS44 | R5 | | | stp | T3 |
| 87 | PL44C | True_OF_PL44D | - | LDQ44 | M5 | | | rst | R4 |
| 88 | PL44B | Comp_OF_PL44A | TRUE | LDQSN44 | T4 | +--------------------+--------+-----------------+
| 90 | PL44D | Comp_OF_PL44C | - | LDQ44 | N5 | | target_usb_diff | | N4 P3 DiffPairs |
| 91 | PL47A | True_OF_PL47B | TRUE | LDQ44 | M6 | +--------------------+--------+-----------------+
| 93 | PL47B | Comp_OF_PL47A | TRUE | LDQ44 | N6 | | target_usb_dp | | N4 |
| 95 | PL47C | True_OF_PL47D | - | LDQ44 | P6 | +--------------------+--------+-----------------+
| 96 | PL47D | Comp_OF_PL47C | - | LDQ44 | P5 | | target_usb_dm | | P3 |
+-----+----------+---------------+------+---------+-----+ +--------------------+--------+-----------------+
| target_type_c | scl | A4 |
| | sda | C4 |
| | int | A3 (PinsN) |
| | fault | D4 (PinsN) |
| | sbu1 | A2 |
| | sbu2 | E4 |
+--------------------+--------+-----------------+
| aux_type_c | scl | H12 |
| | sda | G14 |
| | int | H14 (PinsN) |
| | fault | J14 (PinsN) |
| | sbu1 | H13 |
| | sbu2 | K14 |
+--------------------+--------+-----------------+
| control_vbus_in_en | | K13 (PinsN) |
+--------------------+--------+-----------------+
| aux_vbus_in_en | | L13 (PinsN) |
+--------------------+--------+-----------------+
| target_c_vbus_en | | K5 |
+--------------------+--------+-----------------+
| control_vbus_en | | L1 |
+--------------------+--------+-----------------+
| aux_vbus_en | | L2 |
+--------------------+--------+-----------------+
| target_a_discharge | | K4 |
+--------------------+--------+-----------------+
| power_monitor | scl | D7 |
| | sda | C7 |
| | pwrdn | D5 (PinsN) |
| | slow | C6 |
| | gpio | D6 |
+--------------------+--------+-----------------+
| ram | clk | C3 D3 DiffPairs |
| | dq | F2 B1 C2 E1 |
| | | E3 E2 F3 G4 |
| | rwds | D1 |
| | cs | B2 (PinsN) |
| | reset | C1 (PinsN) |
+--------------------+--------+-----------------+as an svg
rlewkowicz
commented
1 month ago So yeah, I think you get one ram. Literally.
There it is. It's not that, there's only one ram cause I think there's more headers. I know this is probably common knowledge to people here, but it's LITERALLY WIRED, and the wires are PROGRAMMABLE GATES.
Specifically, for memory access, those gates are LITERALLY WIRED to:
C3 D3 F2 B1 C2 E1 E3 E2 F3 G4 D1 B2 C1
Now idk about all of it. Some of those might not goto ram at all. Like the clock pairs? idk if the dif pairs are wired or what kinda gate that is, but idk if thats wired or a timing mechanism.
From there I need to manipulate 12 bytes of memory. I want more. I want the LFE5U-85. Just for the DRAM alone. There is not a copy replace feature š . So I'll have to figure out how to use one header. But then I'm writing a ram handler? I have to go look. I guess I can just expand the current utmi? cram stuff in there. I have to expand a buffer and piggy back somewhere. But I still need aux and I still need to drive the queue.
I want to have the same pipe as analyzer, but know that no matter what queue is running I held it in my hands. I might not fully understand the gates and what I can do yet. But that buffer means it's mine, and I can manipulate it.
rlewkowicz
commented
1 month ago That ram is sd ram and the actually memory call is just the fpga block ram.
It's just an amaranth call. I have a ulxs3 coming. Luna supports it at a glance. But I've got the 85-f variant I think it is coming. Something like 87 bytes of block ram.
Most of the code seems to be verilog though. Theoretically, I can still use this frame work though. I also ordered two USB ports, and the pmod connector that should take it directly to the FPGA. So essentially I'll replicate your hard wired ports.
Replace platform pins on the R4 in the platform code and see where we land.
mossmann
commented
1 month ago I'm having some trouble following you, but it looks like you've correctly realized that there is only one HyperRAM device on the board. The only other RAM available to the FPGA is its (much smaller) internal block RAM.
I'm closing this issue because I believe your questions about the hardware design have been answered. Please open a new issue if you have other questions. This repository is specifically for the board design. If you have further questions about gateware development unrelated to the physical board design, it would be better to ask in https://github.com/greatscottgadgets/cynthion/issues or the GSG Discord.
You use
In your source. What are these? What other ones can I use? I think they correlate to this pin out? I haven't been able to figure it out: https://www.latticesemi.com/view_document?document_id=51576
I'd like to create another ram resource, two actually.