r1.2.0 fails to power on

[mossmann]

The +3V3 supply doesn't come up on r1.2.0 because of unexpected behavior of the FPGA's ~CONTROL_VBUS_IN_EN and ~AUX_VBUS_IN_EN outputs while the supply is ramping up. There is a chance that this could affect revisions prior to r1.2.0, but we haven't seen it happen. We suspect that the pseudo-supply pins added to the FPGA in r1.2.0 make this problem much more likely.

[mossmann]

Simple workaround that removes the option to have the FPGA shut off CONTROL or AUX power inputs: Remove R71 and R78.

Workaround that retains FPGA control of CONTROL or AUX power inputs (but slows down those control signals): Install 1 uF capacitor in place of R72 and R79 and install 20k resistor in place of R71 and R78.

[mossmann]

Planned fix (tested by bodging r1.2.0): Replace Q11 (dual NPN) with dual NAND. Each NAND has a control signal from the FPGA on one input and RC-delayed (20k, 1 uF) +3V3 on the other input.

[mossmann]

Instead of the NAND solution, this was fixed by introducing a ~POWER_GOOD signal in r1.3.0.