Decide on Cynthion flash layout

[antoinevg]

We need to decide on dedicated regions for:

• One or more FPGA bitstreams
• One or more SoC firmware images
• Anything else?

@mossmann has previously suggested the following scheme:

    0x000000 - 0x0000ff jump command
    0x000100 - 0x03ffff reserved
    0x040000 - 0x0effff bitstream slot A (analyzer)
    0x0f0000 - 0x19ffff bitstream slot B (Facedancer)
    0x1a0000 - 0x24ffff bitstream slot C
    0x250000 - 0x2fffff bitstream slot D
    0x300000 - 0x3affff bitstream slot E (fail-safe) (protected)
    0x3b0000 - 0x3ffeff reserved (protected)
    0x3fff00 - 0x3fffff fail-safe jump command (protected)

[antoinevg]

New proposal as of 2024/05/07:

• Install single bitstream at address 0x000000.
• SoC bitstream image will include SoC firmware (appended to bitstream with padding).
• First page-aligned address after the maximum bitstream address: 0x0b0000
  • Flash 0x0b0000 if you want to update firmware