PSRAM/Hyperram peripheral

[schnommus]

Love the work being done on luna-soc.

I don't physically have Cynthion hardware (yet) but was reading through this repo in excitement. I noticed there is an SRAMPeripheral, but was thinking it would be quite nice to also have a memory-mapped PSRAM peripheral for the Hyperram, I'm imagining some crazy Cynthion/LUNA projects using external audio or video pmods where having the extra addressable memory for framebuffers / delay lines could prove quite interesting.

Feel free to close this issue if you feel it's out of scope, just wanted to make a vote for its existence :).

[schnommus]

Hi there @antoinevg -- I had a crack at this and have a working memtest in Rust against a custom Hyperram peripheral

• peripheral: https://github.com/apfelaudio/tiliqua/blob/main/gateware/src/tiliqua/psram_peripheral.py#L107-L208
• (hacky) memtest: https://github.com/apfelaudio/tiliqua/blob/main/gateware/src/example_soc/fw/src/main.rs#L70-L102

I had a look at the Vex bus with an ILA and verified that cache line refills are bursting correctly. There was one small thing in the DQS PHY implementation I had to modify to get the memtest to pass (this might be a real bug?)

• This line: https://github.com/apfelaudio/tiliqua/blob/main/gateware/src/vendor/psram.py#L269

                with m.Elif(self.final_word):
                    m.d.sync += self.phy.clk_en.eq(0) # ADDED: gate clock before last word
                    m.next = 'RECOVERY'

Anyway, just letting you know in case any of this is useful.

Unfortunately I don't have Cynthion hardware yet, so I won't file an upstream PR (I am testing on a different hardware platform but it's still ECP5+hyperram, quite close to the Cynthion).

Probably this shouldn't be upstreamed until the wishbone byte select line is also wired through to the DQS interface, I haven't tested single-byte writes