design r0.6

[mossmann]

• [x] increase PCB size to accommodate future switch from 256 caBGA to 381 caBGA package
• [x] increase clearance around U8, U9, U11 (USB PHYs) to accommodate future switch from USB3343 to USB3320
• [x] rename Sideband port to "Control" and use as primary port for control of both FPGA and Apollo)
• [x] rename Host port to "Aux" for auxiliary functions including MitM
• [x] enhance Target-C PD/CC I/O with FUSB302B or similar Type-C controller
• [x] enhance Aux PD/CC I/O with FUSB302B or similar Type-C controller
• [x] connect shields of all USB connectors together
• [x] disconnect USB shields from GND except through ferrites or 0 ohm resistors (populated by default)
• [x] replace U1, U12, U13 (Target VBUS switches) with FET solution
• [x] add VBUS voltage and current monitoring for all USB ports
• [x] replace D1, D8 (5V diode OR) with FET solution
• [x] move HyperRAM to FPGA pins in a DQS group if possible for both 381 caBGA and 256 caBGA variants
• [x] increase clearance around U6 (microcontroller) to allow future replacement if necessary
• [x] restore 1.8 V supply as an assembly option, supporting either 1.8 V or 3.3 V HyperRAM
• [x] add pin straps for hardware version detection
• [x] increase LED spacing
• [x] add USB switch to Control port
• [x] improve microcontroller D+/D- routing/reference plane
• [x] remove Debug SPI test points
• [x] bigger and better mounting holes
• [x] add third button for SoC reset or general FPGA use
• [x] remove J5 (FPGA JTAG) if it is in the way
• [x] move Pmod connectors to the same side to support 24-pin Pmods
• [x] remove unpopulated SMA connectors
• [x] add FPGA->microcontroller interrupt signal
• [x] add mezzanine connector
• [x] add test points for DFU button
• [x] update layout with all of the above

Close this issue after validating the design and merging to main.

[mossmann]

Work in progress is here: https://github.com/mossmann/luna/tree/hw-r0.6

[yyrfejx884]

Can you add pin headers to target d- and d+ lines?

[martinling]

Can you add pin headers to target d- and d+ lines?

We're not going to be keen to do that, because those lines are used for high-speed differential data, and stubs are a problem for signal integrity. We already have some short stubs in the D+/D- passthrough to connect the target PHY, but they've been minimised as much as possible.

What would you want to do with headers on those pins? In the r0.6 layout there is already a connection for the FPGA to directly sense the target D+/D- signals via some resistors, so if you want to do additional monitoring of those pins, that can be done via the FPGA.

[yyrfejx884]

There are some cases when you need to put some extra circuit on these lines temporarily for example: https://www.huaweinewos.com/huawei-harmonyos-support-harmony-tp-cable.html In this case you need to put two pull-ups on the data lines till the fastboot loads then you can remove them and use the usb as normal.

[mossmann]

There are some cases when you need to put some extra circuit on these lines temporarily for example: https://www.huaweinewos.com/huawei-harmonyos-support-harmony-tp-cable.html In this case you need to put two pull-ups on the data lines till the fastboot loads then you can remove them and use the usb as normal.

We won't be adding a D+/D- pin header in r0.6 for the signal integrity reason @martinling mentioned and also due to lack of board area and time (we have already had r0.6 prototype PCBs made). Harmony TP interfacing will have to be done with an external cable or by soldering resistors to the through-hole TARGET A pins.

If you implement the USB communication with Cynthion (not a passthrough host), you could use the additional TARGET port as a place to plug in a small resistor circuit instead of using a special cable.

[mossmann]

Design validation by hardware bring-up progress:

• [x] scope +3V3
• [x] scope +2V5
• [x] scope +1V1
• [x] scope 60 MHz clock
• [x] check idle current
• [x] SWD via J10
• [x] SWD via J6
• [x] RESET button
• [x] PROGRAM button
• [x] CONTROL USB switch
• [x] Apollo USB data
• [x] program FPGA via Apollo
• [x] debug LEDs
• [x] FPGA LEDs
• [x] interactive-test.py
• [x] bulk_in_speed_test.py on TARGET C
• [x] bulk_in_speed_test.py on AUX
• [x] CONTROL/AUX power input diode OR
• [x] CONTROL overvoltage shutoff
• [x] AUX overvoltage shutoff
• [x] TARGET C VBUS passthrough on/off
• [x] CONTROL VBUS passthrough on/off
• [x] AUX VBUS passthrough on/off
• [x] TARGET C VBUS passthrough on by default while powered off
• [x] TARGET C VBUS passthrough on by default while powered on
• [x] CONTROL VBUS passthrough off by default
• [x] AUX VBUS passthrough off by default
• [x] VBUS passthrough up to 21 V
• [x] VBUS passthrough up to 3 A
• [x] write to SPI flash
• [x] configure FPGA from flash
• [x] high speed USB data passthrough
• [x] bulk_in_speed_test.py on CONTROL
• [x] USER button
• [x] J10 power input
• [x] CONTROL CC Rd
• [x] TARGET C Type-C controller I2C
• [x] TARGET C CC I/O
• [x] TARGET C CC Rd while powered off
• [x] TARGET C CC Rd while powered on
• [x] TARGET C CC overvoltage shutoff
• [x] TARGET C SBU overvoltage shutoff
• [x] TARGET C SBU I/O
• [x] AUX Type-C controller I2C
• [x] AUX CC I/O
• [x] AUX CC Rd while powered off
• [x] AUX CC Rd while powered on
• [x] AUX C CC overvoltage shutoff
• [x] AUX C SBU overvoltage shutoff
• [x] AUX SBU I/O
• [x] power monitor I2C
• [x] CONTROL power monitor
• [x] AUX power monitor
• [x] TARGET A power monitor
• [x] TARGET C power monitor
• [x] CONTROL power input shutoff
• [x] AUX power input shutoff
• [x] PMOD A
• [x] PMOD B
• [x] MEZZANINE
• [x] USB analysis
• [x] CONTROL USB reset detection
• [x] TARGET D+/D- monitor
• [x] +3V3 current up to 1 A
• [x] hyperram_diagnostic.py
• [x] FPGA->MCU interrupt
• [x] TARGET A VBUS discharge

[mossmann]

closing as this (and more) has been merged to: https://github.com/greatscottgadgets/cynthion-hardware