The central clock in r0.1.0 is a 40 MHz TCXO. We want to add the ability to discipline the clock with an external reference clock.
This could be done by switching to a VCXO or VCTCXO such as TXEAACSANF-40.000000 or TG2520SMN 40.0000M-CCGNDM5 and using the FPGA to implement a control loop.
It could even be possible to build our own OCXO with a heating resistor under an RF shield, but we probably wouldn't want to do that on battery power.
Another option would be to use a clock generator such as Si5351C. This would be an easy way to add a great deal of flexibility to the clock architecture, but it would also add phase noise. Si5351C is used on HackRF One. The phase noise there is acceptable, but we hope to achieve lower phase noise with URTI. Other clock generators we've found in the same price range have higher phase noise than Si5351C. See: https://github.com/greatscottgadgets/lab-notes/tree/main/project-reports/2023-06-02-urti-progress-report#clock-generation
The central clock in r0.1.0 is a 40 MHz TCXO. We want to add the ability to discipline the clock with an external reference clock.
This could be done by switching to a VCXO or VCTCXO such as TXEAACSANF-40.000000 or TG2520SMN 40.0000M-CCGNDM5 and using the FPGA to implement a control loop.
We could potentially roll our own VCXO. See:
It could even be possible to build our own OCXO with a heating resistor under an RF shield, but we probably wouldn't want to do that on battery power.
Another option would be to use a clock generator such as Si5351C. This would be an easy way to add a great deal of flexibility to the clock architecture, but it would also add phase noise. Si5351C is used on HackRF One. The phase noise there is acceptable, but we hope to achieve lower phase noise with URTI. Other clock generators we've found in the same price range have higher phase noise than Si5351C. See: https://github.com/greatscottgadgets/lab-notes/tree/main/project-reports/2023-06-02-urti-progress-report#clock-generation