Because the output folder structure is not created, ecpbram fails to create the rand.init file.
On completion of the gateware build there is a small warning:
Hexfiles have different number of words! (0 vs. 1506)
Failed to open input file
But the final message from python suggests that everything was built successfully.
Foboot build complete. Output files:
build/gateware/top.bit Basic Bitstream file. Load this onto the FPGA for testing.
build/gateware/foboot_jtag_spi.svf Loads gateware into FLASH via JTAG
build/gateware/foboot.bit Optimised Bitstream file. (QSPI, Compressed, Higher CLK) Load this into FLASH.
build/gateware/top.svf Serial Vector Format File. Useful when loading over JTAG.
build/gateware/top.v Source Verilog file. Useful for debugging issues.
build/software/include/generated/ Directory with header files for API access.
build/software/bios/bios.elf ELF file for debugging bios.
We'll need to make sure that our output folders are present before before creating the ecpbram init file.
Because the output folder structure is not created, ecpbram fails to create the
rand.initfile.On completion of the gateware build there is a small warning:
But the final message from python suggests that everything was built successfully.
We'll need to make sure that our output folders are present before before creating the ecpbram init file.