Example programs : D, ideas?

[gskielian]

@cliffordwolf @FSMaxB @gordon-quad

We need more examples, what do you all think we need to add? (hoping we could brainstorm, I also have some time this weekend to create stuff)

Some ideas:

• C->Verilog examples for those transitioning from assembly-c mcu workflow. (0b00000001 -> 8'b0000_0001)
• Examples of FPGA Magic/characteristic abilities

-- thoughts?

[gordon-quad]

i could put some sysPLL usage examples with which i experimented recently

[gskielian]

@gordon-quad Awesome : D

[cliffordwolf]

@gordon-quad jfyi: I recently added a icepll tool to icestorm that can be used to calculate the PLL DIVR, DIVF, and DIVQ parameters for a given input/output frequency pair.

[gskielian]

Hi @cliffordwolf, I dove into the http://asic-world.com/verilog/ tutorials and seems that one of my main hurdles coming from C is how to debug -- asic-world had a $default which emulated a printf, but doesn't seem to print to stdout when copypasta'd -- though since I'm new I not sure, maybe this is a feature reserved for a simulator tool?

[cliffordwolf]

@gskielian hmm... $default? Do you mean $display? Yes, this is simulation-only.

Usually you have your design in one verilog file(s) and then a "testbench" in other verilog file(s), that wrap the design. The design should only use features that are synthesizable and the testbench can use all verilog features. For example my PicoRV32 processor core:

• Design: https://github.com/cliffordwolf/picorv32/blob/master/picorv32.v
• Testbench: https://github.com/cliffordwolf/picorv32/blob/master/testbench.v

Yosys can actually evaluate $display (and $finish) statements in initial blocks, as long as everything is constant. This can be used when checking parameters in a module and generating errors when invalid parameters are used. Most other synthesis tools simply ignore all $display statements.

[gordon-quad]

Gentoo ebuilds available at booboo overlay

[gskielian]

@cliffordwolf Awesome, thanks for the clarification : )

I really started to dive into this, dug up all my old FPGA texts and am going to see if I can add some FFT or DSP examples into the mix : )

[gordon-quad]

It would be cool to know how many LUTs required for simple 8x8 multiplier, cos lack of hardware multipliers makes such FPGA not so good for some sofsticated DSP.

[cliffordwolf]

@gordon-quad I just tried it out (running yosys -p synth_ice40 on the following verilog files). This one is 70 LUTs:

module test(input [7:0] a, b, output [7:0] y);
    assign y = a*b;
endmodule

and this one 168 LUTs:

module test(input [7:0] a, b, output [15:0] y);
    assign y = a*b;
endmodule

[gordon-quad]

sad story

[FSMaxB]

A nice example would be something that uses a taster as input (--> debouncing is required). That could be a light running in circles on the LEDs (a register with binary 0001 that gets shifted continuously), with the taster toggling on and off states.

[cliffordwolf]

jfyi: There is now timing analysis in project icestorm (icetime). I have updated the examples that are included in the icestorm source distribution accordingly.