Compile in Windows...?

[jthecodebuilder]

When I finally got my zynq-7000 FPGA, I knew this would be the first community project I had to try out. Only problem is, I have windows, and I technically do have linux installed, but I don't like the idea of taking up another 30GB on my nearly full internal hard drive when I already have Vivado (for Windows) installed on my plenty-of-space external hard drive. Is there a way I could compile this in Windows?

[zephray]

I know that Cygwin + ISE Windows would build many Makefile based fpga projects but I am not sure about Vivado since I do not own any 7-series device boards.

[gtaylormb]

Yeah I see no reason why the build wouldn't work in cygwin. I haven't tried it though.

Greg

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On Dec 27, 2017, 9:56 PM, at 9:56 PM, Wenting Zhang notifications@github.com wrote:

I know that Cygwin + ISE Windows would build many Makefile based fpga projects but I am not sure about Vivado since I do not own any 7-series device boards.

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[jthecodebuilder]

Still kinda at a loss on how to do this, got an Error 2 trying, but zephray said something about ISE Windows? I'm guessing that's PowerShell? Also the BSP file thing required to build opl3_fpga-apps is seemingly gone, mainly cause it seems like you deleted the repository it was in?

[jthecodebuilder]

Actually, the answer was actually in Vivado all along. There is a version of msys (that might be outdated due to the old logo) included that would theoretically let me cross compile code. So I followed the instructions, and as feared, I got to a point in the make process where I can no longer proceed without your technical support. Here's where I'm at right now...

(Also most of the stuff is done so that's why you will see the "Nothing to be done for" stuff.)

$ make cd fpga && make bitstream process_begin: CreateProcess(NULL, sh -c "uname -o 2>/dev/null || echo not", ...) failed. make[1]: Entering directory D:/Xilinx/Vivado/2017.4/msys/home/gmodk_000/opl3_fpga/fpga' make[1]: Nothing to be done forbitstream'. make[1]: Leaving directory D:/Xilinx/Vivado/2017.4/msys/home/gmodk_000/opl3_fpga/fpga' cd software && make make[1]: Entering directoryD:/Xilinx/Vivado/2017.4/msys/home/gmodk_000/opl3_fpga/software' cd opl3_standalone_bsp_0 && make all make[2]: Entering directory D:/Xilinx/Vivado/2017.4/msys/home/gmodk_000/opl3_fpga/software/opl3_standalone_bsp_0' "Running Make include in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_0/src" make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_0/src -s include "SHELL=sh.exe" "COMPILER=arm-xilinx-eabi-gcc" "ARCHIVER=arm-xilinx-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g" make: Interrupt/Exception caught (code = 0xc0000005, addr = 0x41c03d) make[2]: *** [ps7_cortexa9_0/libsrc/coresightps_dcc_v1_0/src/make.include] Error 255 make[2]: Leaving directoryD:/Xilinx/Vivado/2017.4/msys/home/gmodk_000/opl3_fpga/software/opl3_standalone_bsp_0' make[1]: [compile] Error 2 make[1]: Leaving directory `D:/Xilinx/Vivado/2017.4/msys/home/gmodk_000/opl3_fpga/software' make: [all] Error 2

Again, I'm still at a loss here. It seems like there's some sort of interrupt/exception going on here. Might try again with a newer version of msys and see if I have better luck. EDIT: No dice there either.

EDIT 2: Actually, the above error is caused by the SHELL path not being correct, but in this case, I don't know how to change them here, but I have found out that I can still had the Vivado environment in Command Prompt. I ran the settings64 file, corrected the SHELL path to C:\Windows\System32\cmd.exe, cd to the opl3_fpga folder, and tried to run the make process again. As expected, I wasn't able to proceed any further, but this time it's because the Xilink ARM tools are missing. Apparently there is a a Embedded Edition I'm supposed to install to get those, but I'm not sure what to do in Add Design Tools or Devices to do that?

EDIT 3: Apparently they are included with Vivado Design Edition, trying to figure out a way to access them...

EDIT 4: Actually had to go through the lenghy process of installing the ISE, and now when I compile the code, I'm stuck at this... "Compiling coresightps_dcc" arm-xilinx-eabi-ar: ../../../lib/libxil.a: No such file or directory

I hate to admit it, but the more I try to do this by myself, the more hard and frustrating it gets.

(Also, apologies for the long comment, my mind kind of found it easier to just update this one.)

[jthecodebuilder]

I've clearly done enough on my part. Seems like you need to port this project completely to the current Vivado setup so the tedious (and probably deprecated?) ISE is no longer required.

[gtaylormb]

There never were any ISE dependencies. I would suggest stop fighting it and just install Linux.

You can run it under virtualbox.

Greg

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On Dec 31, 2017, 3:16 PM, at 3:16 PM, jthecodebuilder notifications@github.com wrote:

I've clearly done enough on my part. Seems like you need to port this project completely to Vivado so the tedious ISE is no longer required.

-- You are receiving this because you commented. Reply to this email directly or view it on GitHub: https://github.com/gtaylormb/opl3_fpga/issues/11#issuecomment-354621866

[gtaylormb]

Also looks like you're trying to use Vivado 2017.4. The project has not been tested on that version, although it's certainly possible to do so, possibly with some changes. You might first try with 2016.1.

Also make sure you have the Vivado SDK installed.

[jthecodebuilder]

Ok, so I have the Ubuntu VM and the Vivado 2016.1 setup, but when I get to "Compiling coresightps_dcc" I still get arm-xilinx-eabi-ar: ../../../lib/libxil.a: No such file or directory

Now what do I do??

[jthecodebuilder]

I reallly hope this isn't a license issue...

[gtaylormb]

Not a license issue. There was a required empty directory that didn't make the git commit because by default git skips empty directories: software/opl3_standalone_bsp_0/ps7_cortexa9_0/lib

Do a git pull. I've committed the directory.

Greg

[jthecodebuilder]

mfsgen done!

make[1]: Leaving directory '/home/jeremy/opl3_fpga/software' bootgen -image software/bif/sd.bif -o BOOT.bin

Yep, that seems to work now. Thanks! By the way, I have some suggestions for fpga_nes, which I think would be useful.