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gtaylormb / opl3_fpga

Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer
GNU Lesser General Public License v3.0
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Infer async read RAMS in MLABs in Quartus #41

Closed gtaylormb closed 6 months ago

gtaylormb commented 6 months ago

Async 0-cycle read RAMs are now inferred in MLABs in Quartus--substantial savings of ~1000 ALMs. No effect on Xilinx build.