Yosys going belly up for OPL3 System Verilog

gtaylormb / opl3_fpga

Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer

GNU Lesser General Public License v3.0

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Yosys going belly up for OPL3 System Verilog #44

Closed chili-chips-ba closed 3 months ago

chili-chips-ba commented 3 months ago

Hi Guys, as we are porting your design to CologneChip GateMate FPGA, we ran into issues with Yosys and SV.

Any tips and insights you can offer on that subject?

@DadoCCAG, @TarikHamedovic for awareness.

gtaylormb commented 3 months ago

See my comment here: https://github.com/chili-chips-ba/openCologne/issues/3#issuecomment-2156305837

But more in general, if you run into other syntax issues (it appears Yosys doesn't like package imports), I'd push to get these fixes into Yosys as this is your only option for synthesis.

Very cool project by the way!