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gundy / tiny-synth

Verilog code for a simple synth module; developed on TinyFPGA BX
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simpleuart Baud rate error #14

Open RobPearce opened 4 years ago

RobPearce commented 4 years ago

This probably doesn't cause problems at 31.25kBaud off a 16MHz clock, but the Baud rate calculation is wrong. I was trying to reuse the module and testing with 1MBaud off 12MHz (divider of 12) and found that the bits were 14 clocks long. The local parameter "cfg_divider" is set at line 47 to the simple ratio of clock to Baud. At line 142 (also 130, 158, 203) the bit timing counter is tested for being strictly greater than this and, if so, cleared to zero onthenextclock*. Thus with a divider of 12, the counter cycles through from 0 to 13, giving a total of 14 counts. The fix is in two parts. First, change all of those ">" tests to ">=". Second, calculated the cfg_divider as (clk/Baud)-1 (which is very common in hardware UART Baud generator registers).

gundy commented 4 years ago

Hi RobPearce,

Thanks very much for the feedback!

Due to work and other commitments I don't have the time to test this with live hardware, but I've created a branch based on your feedback, and a pull request for it. If you're able to take a look, and are happy with the changes, I'm more than happy to merge them back into the mainline! :-)

Cheers!

RobPearce commented 4 years ago

Hi gundy, I've not built exactly your code (I made trivial changes for my harness) but the changes in that branch match what I did here and I've tested that on real hardware. All looks good at 1MBaud. Cheers, Rob